From 98eb8cb741e0e30f1bcd6f83513abeb8a9002fb4 Mon Sep 17 00:00:00 2001 From: DanielSvoboda Date: Wed, 12 Feb 2025 11:31:19 -0300 Subject: [PATCH] Fix S_LSHR_B32 (#2405) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit the shift value should be extracted from the 5 least significant bits of the second operand (S1.u[4:0]), to ensure that the shift is limited to values ​​from 0 to 31, suitable for 32-bit operations Instruction S_LSHR_B32 Description D.u = S0.u >> S1.u[4:0]. SCC = 1 if result is non-zero. --- src/shader_recompiler/frontend/translate/scalar_alu.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/shader_recompiler/frontend/translate/scalar_alu.cpp b/src/shader_recompiler/frontend/translate/scalar_alu.cpp index b1b260fde..b5c7c98ae 100644 --- a/src/shader_recompiler/frontend/translate/scalar_alu.cpp +++ b/src/shader_recompiler/frontend/translate/scalar_alu.cpp @@ -435,7 +435,8 @@ void Translator::S_LSHL_B64(const GcnInst& inst) { void Translator::S_LSHR_B32(const GcnInst& inst) { const IR::U32 src0{GetSrc(inst.src[0])}; const IR::U32 src1{GetSrc(inst.src[1])}; - const IR::U32 result{ir.ShiftRightLogical(src0, src1)}; + const IR::U32 shift_amt = ir.BitwiseAnd(src1, ir.Imm32(0x1F)); + const IR::U32 result = ir.ShiftRightLogical(src0, shift_amt); SetDst(inst.dst[0], result); ir.SetScc(ir.INotEqual(result, ir.Imm32(0))); }