mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-18 01:14:56 +00:00
shader_recompiler: Small instruction parsing refactor/bugfixes (#340)
* translator: Implemtn f32 to f16 convert * shader_recompiler: Add bit instructions * shader_recompiler: More data share instructions * shader_recompiler: Remove exec contexts, fix S_MOV_B64 * shader_recompiler: Split instruction parsing into categories * shader_recompiler: Better BFS search * shader_recompiler: Constant propagation pass for cmp_class_f32 * shader_recompiler: Partial readfirstlane implementation * shader_recompiler: Stub readlane/writelane only for non-compute * hack: Fix swizzle on RDR * Will properly fix this when merging this * clang format * address_space: Bump user area size to full * shader_recompiler: V_INTERP_MOV_F32 * Should work the same as spirv will emit flat decoration on demand * kernel: Add MAP_OP_MAP_FLEXIBLE * image_view: Attempt to apply storage swizzle on format * vk_scheduler: Barrier attachments on renderpass end * clang format * liverpool: cs state backup * shader_recompiler: More instructions and formats * vector_alu: Proper V_MBCNT_U32_B32 * shader_recompiler: Port some dark souls things * file_system: Implement sceKernelRename * more formats * clang format * resource_tracking_pass: Back to assert * translate: Tracedata * kernel: Remove tracy lock * Solves random crashes in Dark Souls * code: Review comments
This commit is contained in:
TheTurtle
GitHub
parent
ac6dc20c3b
commit
a7c9bfa5c5
66 changed files with 1349 additions and 904 deletions
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@ -16,13 +16,10 @@
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namespace Shader::Gcn {
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std::array<bool, IR::NumScalarRegs> Translator::exec_contexts{};
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Translator::Translator(IR::Block* block_, Info& info_)
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: ir{*block_, block_->begin()}, info{info_} {}
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Translator::Translator(IR::Block* block_, Info& info_, const Profile& profile_)
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: ir{*block_, block_->begin()}, info{info_}, profile{profile_} {}
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void Translator::EmitPrologue() {
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exec_contexts.fill(false);
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ir.Prologue();
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ir.SetExec(ir.Imm1(true));
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@ -97,7 +94,7 @@ IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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}
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break;
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case OperandField::ConstZero:
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if (force_flt) {
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if (is_float) {
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value = ir.Imm32(0.f);
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} else {
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value = ir.Imm32(0U);
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@ -112,14 +109,14 @@ IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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value = ir.Imm32(-s32(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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if (force_flt) {
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if (is_float) {
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value = ir.Imm32(std::bit_cast<float>(operand.code));
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} else {
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value = ir.Imm32(operand.code);
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}
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break;
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case OperandField::ConstFloatPos_1_0:
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if (force_flt) {
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if (is_float) {
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value = ir.Imm32(1.f);
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} else {
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value = ir.Imm32(std::bit_cast<u32>(1.f));
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@ -138,7 +135,11 @@ IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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value = ir.Imm32(-0.5f);
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break;
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case OperandField::ConstFloatNeg_1_0:
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value = ir.Imm32(-1.0f);
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if (is_float) {
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value = ir.Imm32(-1.0f);
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} else {
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value = ir.Imm32(std::bit_cast<u32>(-1.0f));
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}
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break;
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case OperandField::ConstFloatNeg_2_0:
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value = ir.Imm32(-2.0f);
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@ -160,6 +161,8 @@ IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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value = ir.GetVccHi();
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}
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break;
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case OperandField::M0:
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return m0_value;
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default:
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UNREACHABLE();
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}
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@ -336,6 +339,7 @@ void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
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case OperandField::VccHi:
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return ir.SetVccHi(result);
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case OperandField::M0:
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m0_value = result;
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break;
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default:
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UNREACHABLE();
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@ -458,712 +462,84 @@ void Translator::EmitFetch(const GcnInst& inst) {
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}
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}
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void Translate(IR::Block* block, u32 block_base, std::span<const GcnInst> inst_list, Info& info) {
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void Translator::EmitFlowControl(u32 pc, const GcnInst& inst) {
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switch (inst.opcode) {
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case Opcode::S_BARRIER:
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return S_BARRIER();
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case Opcode::S_TTRACEDATA:
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LOG_WARNING(Render_Vulkan, "S_TTRACEDATA instruction!");
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return;
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case Opcode::S_GETPC_B64:
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return S_GETPC_B64(pc, inst);
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case Opcode::S_WAITCNT:
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case Opcode::S_NOP:
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case Opcode::S_ENDPGM:
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case Opcode::S_CBRANCH_EXECZ:
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case Opcode::S_CBRANCH_SCC0:
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case Opcode::S_CBRANCH_SCC1:
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case Opcode::S_CBRANCH_VCCNZ:
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case Opcode::S_CBRANCH_VCCZ:
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case Opcode::S_BRANCH:
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return;
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default:
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UNREACHABLE();
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}
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}
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void Translator::LogMissingOpcode(const GcnInst& inst) {
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const u32 opcode = u32(inst.opcode);
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LOG_ERROR(Render_Recompiler, "Unknown opcode {} ({}, category = {})",
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magic_enum::enum_name(inst.opcode), u32(inst.opcode),
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magic_enum::enum_name(inst.category));
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info.translation_failed = true;
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}
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void Translate(IR::Block* block, u32 pc, std::span<const GcnInst> inst_list, Info& info,
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const Profile& profile) {
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if (inst_list.empty()) {
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return;
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}
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Translator translator{block, info};
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Translator translator{block, info, profile};
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for (const auto& inst : inst_list) {
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block_base += inst.length;
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switch (inst.opcode) {
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case Opcode::S_MOVK_I32:
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translator.S_MOVK(inst);
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break;
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case Opcode::S_MOV_B32:
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translator.S_MOV(inst);
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break;
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case Opcode::S_MUL_I32:
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translator.S_MUL_I32(inst);
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break;
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case Opcode::V_MAD_F32:
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translator.V_MAD_F32(inst);
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break;
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case Opcode::V_MOV_B32:
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translator.V_MOV(inst);
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break;
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case Opcode::V_MAC_F32:
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translator.V_MAC_F32(inst);
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break;
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case Opcode::V_MUL_F32:
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translator.V_MUL_F32(inst);
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break;
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case Opcode::V_AND_B32:
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translator.V_AND_B32(inst);
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break;
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case Opcode::V_OR_B32:
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translator.V_OR_B32(false, inst);
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break;
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case Opcode::V_XOR_B32:
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translator.V_OR_B32(true, inst);
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break;
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case Opcode::V_LSHLREV_B32:
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translator.V_LSHLREV_B32(inst);
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break;
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case Opcode::V_ADD_I32:
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translator.V_ADD_I32(inst);
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break;
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case Opcode::V_ADDC_U32:
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translator.V_ADDC_U32(inst);
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break;
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case Opcode::V_CVT_F32_I32:
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translator.V_CVT_F32_I32(inst);
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break;
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case Opcode::V_CVT_F32_U32:
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translator.V_CVT_F32_U32(inst);
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break;
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case Opcode::V_RCP_F32:
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translator.V_RCP_F32(inst);
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break;
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case Opcode::S_SWAPPC_B64:
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pc += inst.length;
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// Special case for emitting fetch shader.
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if (inst.opcode == Opcode::S_SWAPPC_B64) {
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ASSERT(info.stage == Stage::Vertex);
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translator.EmitFetch(inst);
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break;
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case Opcode::S_WAITCNT:
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break;
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case Opcode::S_LOAD_DWORDX4:
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translator.S_LOAD_DWORD(4, inst);
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break;
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case Opcode::S_LOAD_DWORDX8:
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translator.S_LOAD_DWORD(8, inst);
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break;
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case Opcode::S_LOAD_DWORDX16:
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translator.S_LOAD_DWORD(16, inst);
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break;
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case Opcode::S_BUFFER_LOAD_DWORD:
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translator.S_BUFFER_LOAD_DWORD(1, inst);
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break;
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case Opcode::S_BUFFER_LOAD_DWORDX2:
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translator.S_BUFFER_LOAD_DWORD(2, inst);
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break;
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case Opcode::S_BUFFER_LOAD_DWORDX4:
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translator.S_BUFFER_LOAD_DWORD(4, inst);
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break;
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case Opcode::S_BUFFER_LOAD_DWORDX8:
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translator.S_BUFFER_LOAD_DWORD(8, inst);
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break;
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case Opcode::S_BUFFER_LOAD_DWORDX16:
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translator.S_BUFFER_LOAD_DWORD(16, inst);
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break;
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case Opcode::EXP:
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translator.EXP(inst);
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break;
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case Opcode::V_INTERP_P2_F32:
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translator.V_INTERP_P2_F32(inst);
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break;
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case Opcode::V_CVT_PKRTZ_F16_F32:
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translator.V_CVT_PKRTZ_F16_F32(inst);
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break;
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case Opcode::V_CVT_F32_F16:
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translator.V_CVT_F32_F16(inst);
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break;
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case Opcode::V_CVT_F32_UBYTE0:
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translator.V_CVT_F32_UBYTE(0, inst);
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break;
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case Opcode::V_CVT_F32_UBYTE1:
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translator.V_CVT_F32_UBYTE(1, inst);
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break;
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case Opcode::V_CVT_F32_UBYTE2:
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translator.V_CVT_F32_UBYTE(2, inst);
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break;
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case Opcode::V_CVT_F32_UBYTE3:
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translator.V_CVT_F32_UBYTE(3, inst);
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break;
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case Opcode::V_BFREV_B32:
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translator.V_BFREV_B32(inst);
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break;
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case Opcode::V_LDEXP_F32:
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translator.V_LDEXP_F32(inst);
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break;
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case Opcode::V_FRACT_F32:
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translator.V_FRACT_F32(inst);
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break;
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case Opcode::V_ADD_F32:
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translator.V_ADD_F32(inst);
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break;
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case Opcode::V_CVT_OFF_F32_I4:
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translator.V_CVT_OFF_F32_I4(inst);
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break;
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case Opcode::V_MED3_F32:
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translator.V_MED3_F32(inst);
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break;
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case Opcode::V_FLOOR_F32:
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translator.V_FLOOR_F32(inst);
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break;
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case Opcode::V_SUB_F32:
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translator.V_SUB_F32(inst);
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break;
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case Opcode::V_FMA_F32:
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case Opcode::V_MADAK_F32: // Yes these can share the opcode
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translator.V_FMA_F32(inst);
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break;
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case Opcode::IMAGE_SAMPLE_LZ_O:
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case Opcode::IMAGE_SAMPLE_O:
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case Opcode::IMAGE_SAMPLE_C:
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case Opcode::IMAGE_SAMPLE_C_LZ:
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case Opcode::IMAGE_SAMPLE_LZ:
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case Opcode::IMAGE_SAMPLE:
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case Opcode::IMAGE_SAMPLE_L:
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case Opcode::IMAGE_SAMPLE_C_O:
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case Opcode::IMAGE_SAMPLE_B:
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case Opcode::IMAGE_SAMPLE_C_LZ_O:
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translator.IMAGE_SAMPLE(inst);
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break;
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case Opcode::IMAGE_ATOMIC_ADD:
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translator.IMAGE_ATOMIC(AtomicOp::Add, inst);
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break;
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case Opcode::IMAGE_ATOMIC_AND:
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translator.IMAGE_ATOMIC(AtomicOp::And, inst);
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break;
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case Opcode::IMAGE_ATOMIC_OR:
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translator.IMAGE_ATOMIC(AtomicOp::Or, inst);
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break;
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case Opcode::IMAGE_ATOMIC_XOR:
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translator.IMAGE_ATOMIC(AtomicOp::Xor, inst);
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break;
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case Opcode::IMAGE_ATOMIC_UMAX:
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translator.IMAGE_ATOMIC(AtomicOp::Umax, inst);
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break;
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case Opcode::IMAGE_ATOMIC_SMAX:
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translator.IMAGE_ATOMIC(AtomicOp::Smax, inst);
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break;
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case Opcode::IMAGE_ATOMIC_UMIN:
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translator.IMAGE_ATOMIC(AtomicOp::Umin, inst);
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break;
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case Opcode::IMAGE_ATOMIC_SMIN:
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translator.IMAGE_ATOMIC(AtomicOp::Smin, inst);
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break;
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case Opcode::IMAGE_ATOMIC_INC:
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translator.IMAGE_ATOMIC(AtomicOp::Inc, inst);
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break;
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case Opcode::IMAGE_ATOMIC_DEC:
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translator.IMAGE_ATOMIC(AtomicOp::Dec, inst);
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break;
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case Opcode::IMAGE_GET_LOD:
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translator.IMAGE_GET_LOD(inst);
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break;
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case Opcode::IMAGE_GATHER4_C:
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case Opcode::IMAGE_GATHER4_LZ:
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case Opcode::IMAGE_GATHER4_LZ_O:
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translator.IMAGE_GATHER(inst);
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break;
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case Opcode::IMAGE_STORE:
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translator.IMAGE_STORE(inst);
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break;
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case Opcode::IMAGE_LOAD_MIP:
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translator.IMAGE_LOAD(true, inst);
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break;
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case Opcode::IMAGE_LOAD:
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translator.IMAGE_LOAD(false, inst);
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break;
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case Opcode::V_MAD_U64_U32:
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translator.V_MAD_U64_U32(inst);
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break;
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case Opcode::V_CMP_GE_I32:
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translator.V_CMP_U32(ConditionOp::GE, true, false, inst);
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break;
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case Opcode::V_CMP_EQ_I32:
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translator.V_CMP_U32(ConditionOp::EQ, true, false, inst);
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break;
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case Opcode::V_CMP_LE_I32:
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translator.V_CMP_U32(ConditionOp::LE, true, false, inst);
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break;
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case Opcode::V_CMP_NE_I32:
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translator.V_CMP_U32(ConditionOp::LG, true, false, inst);
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break;
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case Opcode::V_CMP_NE_U32:
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translator.V_CMP_U32(ConditionOp::LG, false, false, inst);
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break;
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case Opcode::V_CMP_EQ_U32:
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translator.V_CMP_U32(ConditionOp::EQ, false, false, inst);
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break;
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case Opcode::V_CMP_F_U32:
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translator.V_CMP_U32(ConditionOp::F, false, false, inst);
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break;
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case Opcode::V_CMP_LT_U32:
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translator.V_CMP_U32(ConditionOp::LT, false, false, inst);
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break;
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case Opcode::V_CMP_GT_U32:
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translator.V_CMP_U32(ConditionOp::GT, false, false, inst);
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break;
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case Opcode::V_CMP_GE_U32:
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translator.V_CMP_U32(ConditionOp::GE, false, false, inst);
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break;
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case Opcode::V_CMP_TRU_U32:
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translator.V_CMP_U32(ConditionOp::TRU, false, false, inst);
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break;
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case Opcode::V_CMP_NEQ_F32:
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translator.V_CMP_F32(ConditionOp::LG, false, inst);
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break;
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case Opcode::V_CMP_F_F32:
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translator.V_CMP_F32(ConditionOp::F, false, inst);
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break;
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case Opcode::V_CMP_LT_F32:
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translator.V_CMP_F32(ConditionOp::LT, false, inst);
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break;
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case Opcode::V_CMP_EQ_F32:
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translator.V_CMP_F32(ConditionOp::EQ, false, inst);
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break;
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case Opcode::V_CMP_LE_F32:
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translator.V_CMP_F32(ConditionOp::LE, false, inst);
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break;
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case Opcode::V_CMP_GT_F32:
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translator.V_CMP_F32(ConditionOp::GT, false, inst);
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break;
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case Opcode::V_CMP_LG_F32:
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translator.V_CMP_F32(ConditionOp::LG, false, inst);
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break;
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case Opcode::V_CMP_GE_F32:
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translator.V_CMP_F32(ConditionOp::GE, false, inst);
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break;
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case Opcode::V_CMP_NLE_F32:
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translator.V_CMP_F32(ConditionOp::GT, false, inst);
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break;
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case Opcode::V_CMP_NLT_F32:
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translator.V_CMP_F32(ConditionOp::GE, false, inst);
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break;
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case Opcode::V_CMP_NGT_F32:
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translator.V_CMP_F32(ConditionOp::LE, false, inst);
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break;
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case Opcode::V_CMP_NGE_F32:
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translator.V_CMP_F32(ConditionOp::LT, false, inst);
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break;
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case Opcode::S_CMP_LT_U32:
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translator.S_CMP(ConditionOp::LT, false, inst);
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break;
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case Opcode::S_CMP_LE_U32:
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translator.S_CMP(ConditionOp::LE, false, inst);
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break;
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case Opcode::S_CMP_LG_U32:
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translator.S_CMP(ConditionOp::LG, false, inst);
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break;
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case Opcode::S_CMP_LT_I32:
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translator.S_CMP(ConditionOp::LT, true, inst);
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break;
|
||||
case Opcode::S_CMP_LG_I32:
|
||||
translator.S_CMP(ConditionOp::LG, true, inst);
|
||||
break;
|
||||
case Opcode::S_CMP_GT_I32:
|
||||
translator.S_CMP(ConditionOp::GT, true, inst);
|
||||
break;
|
||||
case Opcode::S_CMP_GE_I32:
|
||||
translator.S_CMP(ConditionOp::GE, true, inst);
|
||||
break;
|
||||
case Opcode::S_CMP_EQ_I32:
|
||||
translator.S_CMP(ConditionOp::EQ, true, inst);
|
||||
break;
|
||||
case Opcode::S_CMP_EQ_U32:
|
||||
translator.S_CMP(ConditionOp::EQ, false, inst);
|
||||
break;
|
||||
case Opcode::S_LSHL_B32:
|
||||
translator.S_LSHL_B32(inst);
|
||||
break;
|
||||
case Opcode::V_CNDMASK_B32:
|
||||
translator.V_CNDMASK_B32(inst);
|
||||
break;
|
||||
case Opcode::TBUFFER_LOAD_FORMAT_X:
|
||||
translator.BUFFER_LOAD_FORMAT(1, true, true, inst);
|
||||
break;
|
||||
case Opcode::TBUFFER_LOAD_FORMAT_XY:
|
||||
translator.BUFFER_LOAD_FORMAT(2, true, true, inst);
|
||||
break;
|
||||
case Opcode::TBUFFER_LOAD_FORMAT_XYZ:
|
||||
translator.BUFFER_LOAD_FORMAT(3, true, true, inst);
|
||||
break;
|
||||
case Opcode::TBUFFER_LOAD_FORMAT_XYZW:
|
||||
translator.BUFFER_LOAD_FORMAT(4, true, true, inst);
|
||||
break;
|
||||
case Opcode::BUFFER_LOAD_FORMAT_X:
|
||||
translator.BUFFER_LOAD_FORMAT(1, false, true, inst);
|
||||
break;
|
||||
case Opcode::BUFFER_LOAD_FORMAT_XY:
|
||||
translator.BUFFER_LOAD_FORMAT(2, false, true, inst);
|
||||
break;
|
||||
case Opcode::BUFFER_LOAD_FORMAT_XYZ:
|
||||
translator.BUFFER_LOAD_FORMAT(3, false, true, inst);
|
||||
break;
|
||||
case Opcode::BUFFER_LOAD_FORMAT_XYZW:
|
||||
translator.BUFFER_LOAD_FORMAT(4, false, true, inst);
|
||||
break;
|
||||
case Opcode::BUFFER_LOAD_DWORD:
|
||||
translator.BUFFER_LOAD_FORMAT(1, false, false, inst);
|
||||
break;
|
||||
case Opcode::BUFFER_LOAD_DWORDX2:
|
||||
translator.BUFFER_LOAD_FORMAT(2, false, false, inst);
|
||||
break;
|
||||
case Opcode::BUFFER_LOAD_DWORDX3:
|
||||
translator.BUFFER_LOAD_FORMAT(3, false, false, inst);
|
||||
break;
|
||||
case Opcode::BUFFER_LOAD_DWORDX4:
|
||||
translator.BUFFER_LOAD_FORMAT(4, false, false, inst);
|
||||
break;
|
||||
case Opcode::BUFFER_STORE_FORMAT_X:
|
||||
case Opcode::BUFFER_STORE_DWORD:
|
||||
translator.BUFFER_STORE_FORMAT(1, false, inst);
|
||||
break;
|
||||
case Opcode::BUFFER_STORE_DWORDX2:
|
||||
translator.BUFFER_STORE_FORMAT(2, false, inst);
|
||||
break;
|
||||
case Opcode::BUFFER_STORE_DWORDX3:
|
||||
translator.BUFFER_STORE_FORMAT(3, false, inst);
|
||||
break;
|
||||
case Opcode::BUFFER_STORE_FORMAT_XYZW:
|
||||
case Opcode::BUFFER_STORE_DWORDX4:
|
||||
translator.BUFFER_STORE_FORMAT(4, false, inst);
|
||||
break;
|
||||
case Opcode::V_MAX_F32:
|
||||
translator.V_MAX_F32(inst);
|
||||
break;
|
||||
case Opcode::V_MAX_I32:
|
||||
translator.V_MAX_U32(true, inst);
|
||||
break;
|
||||
case Opcode::V_MAX_U32:
|
||||
translator.V_MAX_U32(false, inst);
|
||||
break;
|
||||
case Opcode::V_NOT_B32:
|
||||
translator.V_NOT_B32(inst);
|
||||
break;
|
||||
case Opcode::V_RSQ_F32:
|
||||
translator.V_RSQ_F32(inst);
|
||||
break;
|
||||
case Opcode::S_ANDN2_B64:
|
||||
translator.S_AND_B64(NegateMode::Src1, inst);
|
||||
break;
|
||||
case Opcode::S_ORN2_B64:
|
||||
translator.S_OR_B64(NegateMode::Src1, false, inst);
|
||||
break;
|
||||
case Opcode::V_SIN_F32:
|
||||
translator.V_SIN_F32(inst);
|
||||
break;
|
||||
case Opcode::V_COS_F32:
|
||||
translator.V_COS_F32(inst);
|
||||
break;
|
||||
case Opcode::V_LOG_F32:
|
||||
translator.V_LOG_F32(inst);
|
||||
break;
|
||||
case Opcode::V_EXP_F32:
|
||||
translator.V_EXP_F32(inst);
|
||||
break;
|
||||
case Opcode::V_SQRT_F32:
|
||||
translator.V_SQRT_F32(inst);
|
||||
break;
|
||||
case Opcode::V_MIN_F32:
|
||||
translator.V_MIN_F32(inst);
|
||||
break;
|
||||
case Opcode::V_MIN_I32:
|
||||
translator.V_MIN_I32(inst);
|
||||
break;
|
||||
case Opcode::V_MIN3_F32:
|
||||
translator.V_MIN3_F32(inst);
|
||||
break;
|
||||
case Opcode::V_MIN_LEGACY_F32:
|
||||
translator.V_MIN_F32(inst, true);
|
||||
break;
|
||||
case Opcode::V_MADMK_F32:
|
||||
translator.V_MADMK_F32(inst);
|
||||
break;
|
||||
case Opcode::V_CUBEMA_F32:
|
||||
translator.V_CUBEMA_F32(inst);
|
||||
break;
|
||||
case Opcode::V_CUBESC_F32:
|
||||
translator.V_CUBESC_F32(inst);
|
||||
break;
|
||||
case Opcode::V_CUBETC_F32:
|
||||
translator.V_CUBETC_F32(inst);
|
||||
break;
|
||||
case Opcode::V_CUBEID_F32:
|
||||
translator.V_CUBEID_F32(inst);
|
||||
break;
|
||||
case Opcode::V_CVT_U32_F32:
|
||||
translator.V_CVT_U32_F32(inst);
|
||||
break;
|
||||
case Opcode::V_CVT_I32_F32:
|
||||
translator.V_CVT_I32_F32(inst);
|
||||
break;
|
||||
case Opcode::V_CVT_FLR_I32_F32:
|
||||
translator.V_CVT_FLR_I32_F32(inst);
|
||||
break;
|
||||
case Opcode::V_SUBREV_F32:
|
||||
translator.V_SUBREV_F32(inst);
|
||||
break;
|
||||
case Opcode::S_AND_SAVEEXEC_B64:
|
||||
translator.S_AND_SAVEEXEC_B64(inst);
|
||||
break;
|
||||
case Opcode::S_MOV_B64:
|
||||
translator.S_MOV_B64(inst);
|
||||
break;
|
||||
case Opcode::V_SUBREV_I32:
|
||||
translator.V_SUBREV_I32(inst);
|
||||
break;
|
||||
continue;
|
||||
}
|
||||
|
||||
case Opcode::V_CMPX_F_F32:
|
||||
translator.V_CMP_F32(ConditionOp::F, true, inst);
|
||||
// Emit instructions for each category.
|
||||
switch (inst.category) {
|
||||
case InstCategory::DataShare:
|
||||
translator.EmitDataShare(inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_LT_F32:
|
||||
translator.V_CMP_F32(ConditionOp::LT, true, inst);
|
||||
case InstCategory::VectorInterpolation:
|
||||
translator.EmitVectorInterpolation(inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_EQ_F32:
|
||||
translator.V_CMP_F32(ConditionOp::EQ, true, inst);
|
||||
case InstCategory::ScalarMemory:
|
||||
translator.EmitScalarMemory(inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_LE_F32:
|
||||
translator.V_CMP_F32(ConditionOp::LE, true, inst);
|
||||
case InstCategory::VectorMemory:
|
||||
translator.EmitVectorMemory(inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_GT_F32:
|
||||
translator.V_CMP_F32(ConditionOp::GT, true, inst);
|
||||
case InstCategory::Export:
|
||||
translator.EmitExport(inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_LG_F32:
|
||||
translator.V_CMP_F32(ConditionOp::LG, true, inst);
|
||||
case InstCategory::FlowControl:
|
||||
translator.EmitFlowControl(pc, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_GE_F32:
|
||||
translator.V_CMP_F32(ConditionOp::GE, true, inst);
|
||||
case InstCategory::ScalarALU:
|
||||
translator.EmitScalarAlu(inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_NGE_F32:
|
||||
translator.V_CMP_F32(ConditionOp::LT, true, inst);
|
||||
case InstCategory::VectorALU:
|
||||
translator.EmitVectorAlu(inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_NLG_F32:
|
||||
translator.V_CMP_F32(ConditionOp::EQ, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_NGT_F32:
|
||||
translator.V_CMP_F32(ConditionOp::LE, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_NLE_F32:
|
||||
translator.V_CMP_F32(ConditionOp::GT, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_NEQ_F32:
|
||||
translator.V_CMP_F32(ConditionOp::LG, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_NLT_F32:
|
||||
translator.V_CMP_F32(ConditionOp::GE, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_TRU_F32:
|
||||
translator.V_CMP_F32(ConditionOp::TRU, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMP_LE_U32:
|
||||
translator.V_CMP_U32(ConditionOp::LE, false, false, inst);
|
||||
break;
|
||||
case Opcode::V_CMP_GT_I32:
|
||||
translator.V_CMP_U32(ConditionOp::GT, true, false, inst);
|
||||
break;
|
||||
case Opcode::V_CMP_LT_I32:
|
||||
translator.V_CMP_U32(ConditionOp::LT, true, false, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_LT_I32:
|
||||
translator.V_CMP_U32(ConditionOp::LT, true, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_F_U32:
|
||||
translator.V_CMP_U32(ConditionOp::F, false, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_LT_U32:
|
||||
translator.V_CMP_U32(ConditionOp::LT, false, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_EQ_U32:
|
||||
translator.V_CMP_U32(ConditionOp::EQ, false, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_LE_U32:
|
||||
translator.V_CMP_U32(ConditionOp::LE, false, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_GT_U32:
|
||||
translator.V_CMP_U32(ConditionOp::GT, false, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_NE_U32:
|
||||
translator.V_CMP_U32(ConditionOp::LG, false, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_GE_U32:
|
||||
translator.V_CMP_U32(ConditionOp::GE, false, true, inst);
|
||||
break;
|
||||
case Opcode::V_CMPX_TRU_U32:
|
||||
translator.V_CMP_U32(ConditionOp::TRU, false, true, inst);
|
||||
break;
|
||||
case Opcode::S_OR_B64:
|
||||
translator.S_OR_B64(NegateMode::None, false, inst);
|
||||
break;
|
||||
case Opcode::S_NOR_B64:
|
||||
translator.S_OR_B64(NegateMode::Result, false, inst);
|
||||
break;
|
||||
case Opcode::S_XOR_B64:
|
||||
translator.S_OR_B64(NegateMode::None, true, inst);
|
||||
break;
|
||||
case Opcode::S_AND_B64:
|
||||
translator.S_AND_B64(NegateMode::None, inst);
|
||||
break;
|
||||
case Opcode::S_NOT_B64:
|
||||
translator.S_NOT_B64(inst);
|
||||
break;
|
||||
case Opcode::S_NAND_B64:
|
||||
translator.S_AND_B64(NegateMode::Result, inst);
|
||||
break;
|
||||
case Opcode::V_LSHRREV_B32:
|
||||
translator.V_LSHRREV_B32(inst);
|
||||
break;
|
||||
case Opcode::S_ADD_I32:
|
||||
translator.S_ADD_I32(inst);
|
||||
break;
|
||||
case Opcode::V_MUL_HI_U32:
|
||||
translator.V_MUL_HI_U32(false, inst);
|
||||
break;
|
||||
case Opcode::V_MUL_LO_I32:
|
||||
translator.V_MUL_LO_U32(inst);
|
||||
break;
|
||||
case Opcode::V_SAD_U32:
|
||||
translator.V_SAD_U32(inst);
|
||||
break;
|
||||
case Opcode::V_BFE_U32:
|
||||
translator.V_BFE_U32(false, inst);
|
||||
break;
|
||||
case Opcode::V_BFE_I32:
|
||||
translator.V_BFE_U32(true, inst);
|
||||
break;
|
||||
case Opcode::V_MAD_I32_I24:
|
||||
translator.V_MAD_I32_I24(inst);
|
||||
break;
|
||||
case Opcode::V_MUL_I32_I24:
|
||||
case Opcode::V_MUL_U32_U24:
|
||||
translator.V_MUL_I32_I24(inst);
|
||||
break;
|
||||
case Opcode::V_SUB_I32:
|
||||
translator.V_SUB_I32(inst);
|
||||
break;
|
||||
case Opcode::V_LSHR_B32:
|
||||
translator.V_LSHR_B32(inst);
|
||||
break;
|
||||
case Opcode::V_ASHRREV_I32:
|
||||
translator.V_ASHRREV_I32(inst);
|
||||
break;
|
||||
case Opcode::V_MAD_U32_U24:
|
||||
translator.V_MAD_U32_U24(inst);
|
||||
break;
|
||||
case Opcode::S_AND_B32:
|
||||
translator.S_AND_B32(inst);
|
||||
break;
|
||||
case Opcode::S_ASHR_I32:
|
||||
translator.S_ASHR_I32(inst);
|
||||
break;
|
||||
case Opcode::S_OR_B32:
|
||||
translator.S_OR_B32(inst);
|
||||
break;
|
||||
case Opcode::S_LSHR_B32:
|
||||
translator.S_LSHR_B32(inst);
|
||||
break;
|
||||
case Opcode::S_CSELECT_B32:
|
||||
translator.S_CSELECT_B32(inst);
|
||||
break;
|
||||
case Opcode::S_CSELECT_B64:
|
||||
translator.S_CSELECT_B64(inst);
|
||||
break;
|
||||
case Opcode::S_BFE_U32:
|
||||
translator.S_BFE_U32(inst);
|
||||
break;
|
||||
case Opcode::V_RNDNE_F32:
|
||||
translator.V_RNDNE_F32(inst);
|
||||
break;
|
||||
case Opcode::V_BCNT_U32_B32:
|
||||
translator.V_BCNT_U32_B32(inst);
|
||||
break;
|
||||
case Opcode::V_MAX3_F32:
|
||||
translator.V_MAX3_F32(inst);
|
||||
break;
|
||||
case Opcode::DS_SWIZZLE_B32:
|
||||
translator.DS_SWIZZLE_B32(inst);
|
||||
break;
|
||||
case Opcode::V_MUL_LO_U32:
|
||||
translator.V_MUL_LO_U32(inst);
|
||||
break;
|
||||
case Opcode::S_BFM_B32:
|
||||
translator.S_BFM_B32(inst);
|
||||
break;
|
||||
case Opcode::V_MIN_U32:
|
||||
translator.V_MIN_U32(inst);
|
||||
break;
|
||||
case Opcode::V_CMP_NE_U64:
|
||||
translator.V_CMP_NE_U64(inst);
|
||||
break;
|
||||
case Opcode::V_CMP_CLASS_F32:
|
||||
translator.V_CMP_CLASS_F32(inst);
|
||||
break;
|
||||
case Opcode::V_TRUNC_F32:
|
||||
translator.V_TRUNC_F32(inst);
|
||||
break;
|
||||
case Opcode::V_CEIL_F32:
|
||||
translator.V_CEIL_F32(inst);
|
||||
break;
|
||||
case Opcode::V_BFI_B32:
|
||||
translator.V_BFI_B32(inst);
|
||||
break;
|
||||
case Opcode::S_BREV_B32:
|
||||
translator.S_BREV_B32(inst);
|
||||
break;
|
||||
case Opcode::S_ADD_U32:
|
||||
translator.S_ADD_U32(inst);
|
||||
break;
|
||||
case Opcode::S_ADDC_U32:
|
||||
translator.S_ADDC_U32(inst);
|
||||
break;
|
||||
case Opcode::S_SUB_U32:
|
||||
case Opcode::S_SUB_I32:
|
||||
translator.S_SUB_U32(inst);
|
||||
break;
|
||||
// TODO: Separate implementation for legacy variants.
|
||||
case Opcode::V_MUL_LEGACY_F32:
|
||||
translator.V_MUL_F32(inst);
|
||||
break;
|
||||
case Opcode::V_MAC_LEGACY_F32:
|
||||
translator.V_MAC_F32(inst);
|
||||
break;
|
||||
case Opcode::V_MAD_LEGACY_F32:
|
||||
translator.V_MAD_F32(inst);
|
||||
break;
|
||||
case Opcode::V_MAX_LEGACY_F32:
|
||||
translator.V_MAX_F32(inst, true);
|
||||
break;
|
||||
case Opcode::V_RSQ_LEGACY_F32:
|
||||
case Opcode::V_RSQ_CLAMP_F32:
|
||||
translator.V_RSQ_F32(inst);
|
||||
break;
|
||||
case Opcode::V_RCP_IFLAG_F32:
|
||||
translator.V_RCP_F32(inst);
|
||||
break;
|
||||
case Opcode::IMAGE_GET_RESINFO:
|
||||
translator.IMAGE_GET_RESINFO(inst);
|
||||
break;
|
||||
case Opcode::S_BARRIER:
|
||||
translator.S_BARRIER();
|
||||
break;
|
||||
case Opcode::S_TTRACEDATA:
|
||||
LOG_WARNING(Render_Vulkan, "S_TTRACEDATA instruction!");
|
||||
break;
|
||||
case Opcode::DS_READ_B32:
|
||||
translator.DS_READ(32, false, false, inst);
|
||||
break;
|
||||
case Opcode::DS_READ2_B32:
|
||||
translator.DS_READ(32, false, true, inst);
|
||||
break;
|
||||
case Opcode::DS_WRITE_B32:
|
||||
translator.DS_WRITE(32, false, false, inst);
|
||||
break;
|
||||
case Opcode::DS_WRITE2_B32:
|
||||
translator.DS_WRITE(32, false, true, inst);
|
||||
break;
|
||||
case Opcode::V_READFIRSTLANE_B32:
|
||||
translator.V_READFIRSTLANE_B32(inst);
|
||||
break;
|
||||
case Opcode::S_GETPC_B64:
|
||||
translator.S_GETPC_B64(block_base, inst);
|
||||
break;
|
||||
case Opcode::S_NOP:
|
||||
case Opcode::S_CBRANCH_EXECZ:
|
||||
case Opcode::S_CBRANCH_SCC0:
|
||||
case Opcode::S_CBRANCH_SCC1:
|
||||
case Opcode::S_CBRANCH_VCCNZ:
|
||||
case Opcode::S_CBRANCH_VCCZ:
|
||||
case Opcode::S_BRANCH:
|
||||
case Opcode::S_WQM_B64:
|
||||
case Opcode::V_INTERP_P1_F32:
|
||||
case Opcode::S_ENDPGM:
|
||||
case InstCategory::DebugProfile:
|
||||
break;
|
||||
default:
|
||||
const u32 opcode = u32(inst.opcode);
|
||||
LOG_ERROR(Render_Recompiler, "Unknown opcode {} ({})",
|
||||
magic_enum::enum_name(inst.opcode), opcode);
|
||||
info.translation_failed = true;
|
||||
UNREACHABLE();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue