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video_core: Fix a few problems

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IndecisiveTurtle 2024-06-29 16:44:39 +03:00 • committed by TheTurtle
parent 114f06d3f2
commit ad10020836
10 changed files with 89 additions and 49 deletions
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5
src/shader_recompiler/frontend/translate/translate.cpp
View file

@ -328,6 +328,7 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
translator.V_FMA_F32(inst);
break;
case Opcode::IMAGE_SAMPLE_LZ_O:
case Opcode::IMAGE_SAMPLE_O:
case Opcode::IMAGE_SAMPLE_C_LZ:
case Opcode::IMAGE_SAMPLE_LZ:
case Opcode::IMAGE_SAMPLE:
@ -455,6 +456,7 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
translator.BUFFER_LOAD_FORMAT(4, false, inst);
break;
case Opcode::BUFFER_STORE_FORMAT_X:
case Opcode::BUFFER_STORE_DWORD:
translator.BUFFER_STORE_FORMAT(1, false, inst);
break;
case Opcode::BUFFER_STORE_FORMAT_XYZW:
@ -469,6 +471,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
case Opcode::V_MAX_U32:
translator.V_MAX_U32(false, inst);
break;
case Opcode::V_NOT_B32:
translator.V_NOT_B32(inst);
break;
case Opcode::V_RSQ_F32:
translator.V_RSQ_F32(inst);
break;

1
src/shader_recompiler/frontend/translate/translate.h
View file

@ -129,6 +129,7 @@ public:
void V_MIN_U32(const GcnInst& inst);
void V_CMP_NE_U64(const GcnInst& inst);
void V_BFI_B32(const GcnInst& inst);
void V_NOT_B32(const GcnInst& inst);
// Vector Memory
void BUFFER_LOAD_FORMAT(u32 num_dwords, bool is_typed, const GcnInst& inst);

10
src/shader_recompiler/frontend/translate/vector_alu.cpp
View file

@ -46,7 +46,10 @@ void Translator::V_CNDMASK_B32(const GcnInst& inst) {
const bool has_flt_source =
is_float_const(inst.src[0].field) || is_float_const(inst.src[1].field);
const IR::U32F32 src0 = GetSrc(inst.src[0], has_flt_source);
const IR::U32F32 src1 = GetSrc(inst.src[1], has_flt_source);
IR::U32F32 src1 = GetSrc(inst.src[1], has_flt_source);
if (src0.Type() == IR::Type::F32 && src1.Type() == IR::Type::U32) {
src1 = ir.BitCast<IR::F32, IR::U32>(src1);
}
const IR::Value result = ir.Select(flag, src1, src0);
ir.SetVectorReg(dst_reg, IR::U32F32{result});
}
@ -478,4 +481,9 @@ void Translator::V_BFI_B32(const GcnInst& inst) {
ir.BitwiseOr(ir.BitwiseAnd(src0, src1), ir.BitwiseAnd(ir.BitwiseNot(src0), src2)));
}
void Translator::V_NOT_B32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
SetDst(inst.dst[0], ir.BitwiseNot(src0));
}
} // namespace Shader::Gcn