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video_core: Add basic command list processing (#117)
This commit is contained in:
parent
2696733cad
commit
b94efcba5a
18 changed files with 1560 additions and 163 deletions
647
src/video_core/amdgpu/liverpool.h
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647
src/video_core/amdgpu/liverpool.h
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include <array>
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#include "common/bit_field.h"
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#include "common/types.h"
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namespace AmdGpu {
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#define GFX6_3D_REG_INDEX(field_name) (offsetof(AmdGpu::Liverpool::Regs, field_name) / sizeof(u32))
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#define CONCAT2(x, y) DO_CONCAT2(x, y)
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#define DO_CONCAT2(x, y) x##y
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#define INSERT_PADDING_WORDS(num_words) \
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[[maybe_unused]] std::array<u32, num_words> CONCAT2(pad, __LINE__)
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struct Liverpool {
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static constexpr u32 NumColorBuffers = 8;
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static constexpr u32 NumViewports = 16;
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static constexpr u32 NumClipPlanes = 6;
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static constexpr u32 NumWordsShaderUserData = 16;
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static constexpr u32 UconfigRegWordOffset = 0xC000;
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static constexpr u32 ContextRegWordOffset = 0xA000;
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static constexpr u32 ShRegWordOffset = 0x2C00;
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static constexpr u32 NumRegs = 0xD000;
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using UserData = std::array<u32, NumWordsShaderUserData>;
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struct ShaderProgram {
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u32 address_lo;
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u32 address_hi;
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union {
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BitField<0, 6, u64> num_vgprs;
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BitField<6, 4, u64> num_sgprs;
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BitField<33, 5, u64> num_user_regs;
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} settings;
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UserData user_data;
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const u8* Address() const {
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const uintptr_t addr = uintptr_t(address_hi) << 40 | uintptr_t(address_lo) << 8;
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return reinterpret_cast<const u8*>(addr);
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}
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};
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enum class ShaderExportComp : u32 {
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None = 0,
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OneComp = 1,
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TwoComp = 2,
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FourCompCompressed = 3,
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FourComp = 4,
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};
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union ShaderPosFormat {
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u32 raw;
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BitField<0, 4, ShaderExportComp> pos0;
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BitField<4, 4, ShaderExportComp> pos1;
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BitField<8, 4, ShaderExportComp> pos2;
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BitField<12, 4, ShaderExportComp> pos3;
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};
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enum class ShaderExportFormat : u32 {
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Zero = 0,
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R_32 = 1,
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GR_32 = 2,
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AR_32 = 3,
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ABGR_FP16 = 4,
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ABGR_UNORM16 = 5,
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ABGR_SNORM16 = 6,
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ABGR_UINT16 = 7,
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ABGR_SINT16 = 8,
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ABGR_32 = 9,
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};
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union ColorExportFormat {
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u32 raw;
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BitField<0, 4, ShaderExportFormat> col0;
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BitField<4, 4, ShaderExportFormat> col1;
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BitField<8, 4, ShaderExportFormat> col2;
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BitField<12, 4, ShaderExportFormat> col3;
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BitField<16, 4, ShaderExportFormat> col4;
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BitField<20, 4, ShaderExportFormat> col5;
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BitField<24, 4, ShaderExportFormat> col6;
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BitField<28, 4, ShaderExportFormat> col7;
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};
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union VsOutputControl {
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u32 raw;
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BitField<0, 8, u32> clip_distance_enable;
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BitField<8, 8, u32> cull_distance_enable;
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BitField<16, 1, u32> use_vtx_point_size;
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BitField<17, 1, u32> use_vtx_edge_flag;
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BitField<18, 1, u32> use_vtx_render_target_idx;
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BitField<19, 1, u32> use_vtx_viewport_idx;
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BitField<20, 1, u32> use_vtx_kill_flag;
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bool IsClipDistEnabled(u32 index) const {
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return (clip_distance_enable.Value() >> index) & 1;
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}
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bool IsCullDistEnabled(u32 index) const {
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return (cull_distance_enable.Value() >> index) & 1;
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}
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};
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enum class ZOrder : u32 {
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LateZ = 0,
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EarlyZLateZ = 1,
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ReZ = 2,
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EarlyZReZ = 3,
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};
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enum class ConservativeDepth : u32 {
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Any = 0,
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LessThanZ = 1,
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GreaterThanZ = 2,
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};
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union DepthBufferControl {
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u32 raw;
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BitField<0, 1, u32> z_export_enable;
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BitField<1, 1, u32> stencil_test_val_export_enable;
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BitField<2, 1, u32> stencil_op_val_export_enable;
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BitField<4, 2, ZOrder> z_order;
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BitField<6, 1, u32> kill_enable;
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BitField<7, 1, u32> coverage_to_mask_enable;
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BitField<8, 1, u32> mask_export_enable;
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BitField<9, 1, u32> exec_on_hier_fail;
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BitField<10, 1, u32> exec_on_noop;
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BitField<11, 1, u32> alpha_to_mask_disable;
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BitField<12, 1, u32> depth_before_shader;
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BitField<13, 2, ConservativeDepth> conservative_z_export;
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};
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enum class CompareFunc : u32 {
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Never = 0,
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Less = 1,
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Equal = 2,
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LessEqual = 3,
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Greater = 4,
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NotEqual = 5,
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GreaterEqual = 6,
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Always = 7,
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};
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union DepthControl {
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u32 raw;
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BitField<0, 1, u32> stencil_enable;
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BitField<1, 1, u32> depth_enable;
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BitField<2, 1, u32> depth_write_enable;
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BitField<3, 1, u32> depth_bounds_enable;
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BitField<4, 3, CompareFunc> depth_func;
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BitField<7, 1, u32> backface_enable;
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BitField<8, 3, CompareFunc> stencil_ref_func;
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BitField<20, 3, CompareFunc> stencil_bf_func;
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BitField<30, 1, u32> enable_color_writes_on_depth_fail;
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BitField<31, 1, u32> disable_color_writes_on_depth_pass;
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};
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union DepthSize {
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u32 raw;
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BitField<0, 11, u32> pitch_tile_max;
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BitField<11, 11, u32> height_tile_max;
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u32 Pitch() const {
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return (pitch_tile_max + 1) << 3;
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}
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u32 Height() const {
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return (height_tile_max + 1) << 3;
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}
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};
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union DepthSlice {
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u32 raw;
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BitField<0, 22, u32> slice_tile_max;
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};
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enum class StencilFunc : u32 {
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Keep = 0,
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Zero = 1,
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Ones = 2,
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ReplaceTest = 3,
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ReplaceOp = 4,
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AddClamp = 5,
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SubClamp = 6,
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Invert = 7,
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AddWrap = 8,
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SubWrap = 9,
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And = 10,
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Or = 11,
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Xor = 12,
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Nand = 13,
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Nor = 14,
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Xnor = 15,
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};
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union StencilControl {
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u32 raw;
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BitField<0, 4, StencilFunc> stencil_fail_front;
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BitField<4, 4, StencilFunc> stencil_zpass_front;
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BitField<8, 4, StencilFunc> stencil_zfail_front;
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BitField<12, 4, StencilFunc> stencil_fail_back;
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BitField<16, 4, StencilFunc> stencil_zpass_back;
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BitField<20, 4, StencilFunc> stencil_zfail_back;
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};
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union StencilRefMask {
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u32 raw;
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BitField<0, 8, u32> stencil_test_val;
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BitField<8, 8, u32> stencil_mask;
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BitField<16, 8, u32> stencil_write_mask;
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BitField<24, 8, u32> stencil_op_val;
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};
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union StencilInfo {
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u32 raw;
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BitField<0, 1, u32> format;
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};
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enum class ClipSpace : u32 {
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MinusWToW = 0,
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ZeroToW = 1,
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};
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enum class PrimKillCond : u32 {
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AllVtx = 0,
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AnyVtx = 1,
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};
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union ClipperControl {
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u32 raw;
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BitField<0, 6, u32> user_clip_plane_enable;
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BitField<16, 1, u32> clip_disable;
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BitField<19, 1, ClipSpace> clip_space;
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BitField<21, 1, PrimKillCond> vtx_kill_or;
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BitField<22, 1, u32> dx_rasterization_kill;
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BitField<23, 1, u32> dx_linear_attr_clip_enable;
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BitField<26, 1, u32> zclip_near_disable;
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BitField<26, 1, u32> zclip_far_disable;
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};
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enum class PolygonMode : u32 {
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Point = 0,
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Line = 1,
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Fill = 2,
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};
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enum class ProvokingVtxLast : u32 {
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First = 0,
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Last = 1,
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};
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enum class CullMode : u32 {
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None = 0,
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Front = 1,
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Back = 2,
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FrontAndBack = 3,
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};
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union PolygonControl {
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u32 raw;
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BitField<0, 1, u32> cull_front;
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BitField<1, 1, u32> cull_back;
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BitField<3, 2, u32> enable_polygon_mode;
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BitField<5, 3, PolygonMode> polygon_mode_front;
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BitField<8, 3, PolygonMode> polygon_mode_back;
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BitField<11, 1, u32> enable_polygon_offset_front;
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BitField<12, 1, u32> enable_polygon_offset_back;
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BitField<13, 1, u32> enable_polygon_offset_para;
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BitField<13, 1, u32> enable_window_offset;
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BitField<19, 1, ProvokingVtxLast> provoking_vtx_last;
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PolygonMode PolyMode() const {
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return enable_polygon_mode ? polygon_mode_front.Value() : PolygonMode::Fill;
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}
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CullMode CullingMode() const {
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return static_cast<CullMode>(cull_front | cull_back << 1);
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}
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};
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union VsOutputConfig {
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u32 raw;
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BitField<1, 5, u32> export_count_min_one;
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BitField<6, 1, u32> half_pack;
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u32 NumExports() const {
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return export_count_min_one.Value() + 1;
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}
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};
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union ColorBufferMask {
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u32 raw;
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BitField<0, 4, u32> output0_mask;
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BitField<4, 4, u32> output1_mask;
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BitField<8, 4, u32> output2_mask;
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BitField<12, 4, u32> output3_mask;
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BitField<16, 4, u32> output4_mask;
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BitField<20, 4, u32> output5_mask;
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BitField<24, 4, u32> output6_mask;
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BitField<28, 4, u32> output7_mask;
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};
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struct IndexBufferBase {
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BitField<0, 8, u32> base_addr_hi;
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u32 base_addr_lo;
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VAddr Address() const {
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return base_addr_lo | u64(base_addr_hi) << 32;
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}
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};
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enum class IndexType : u32 {
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Index16 = 0,
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Index32 = 1,
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};
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enum class IndexSwapMode : u32 {
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None = 0,
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Swap16 = 1,
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Swap32 = 2,
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SwapWord = 3,
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};
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union IndexBufferType {
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u32 raw;
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BitField<0, 2, IndexType> index_type;
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BitField<2, 2, IndexSwapMode> swap_mode;
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};
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union VgtNumInstances {
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u32 num_instances;
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u32 NumInstances() const {
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return num_instances == 0 ? 1 : num_instances;
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}
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};
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struct Scissor {
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union {
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BitField<0, 16, s32> top_left_x;
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BitField<16, 16, s32> top_left_y;
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};
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union {
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BitField<0, 15, u32> bottom_right_x;
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BitField<16, 15, u32> bottom_right_y;
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};
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u32 GetWidth() const {
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return static_cast<u32>(bottom_right_x - top_left_x);
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}
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u32 GetHeight() const {
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return static_cast<u32>(bottom_right_y - top_left_y);
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}
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};
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struct ViewportScissor {
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union {
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BitField<0, 15, s32> top_left_x;
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BitField<15, 15, s32> top_left_y;
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BitField<30, 1, s32> window_offset_disble;
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};
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union {
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BitField<0, 15, s32> bottom_right_x;
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BitField<15, 15, s32> bottom_right_y;
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};
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};
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struct ViewportDepth {
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float zmin;
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float zmax;
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};
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struct ViewportBounds {
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float xscale;
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float xoffset;
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float yscale;
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float yoffset;
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float zoffset;
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float zscale;
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};
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union ViewportControl {
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BitField<0, 1, u32> xscale_enable;
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BitField<1, 1, u32> xoffset_enable;
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BitField<2, 1, u32> yscale_enable;
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BitField<3, 1, u32> yoffset_enable;
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BitField<4, 1, u32> zscale_enable;
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BitField<5, 1, u32> zoffset_enable;
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BitField<8, 1, u32> xy_transformed;
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BitField<9, 1, u32> z_transformed;
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BitField<10, 1, u32> w_transformed;
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};
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struct ClipUserData {
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u32 data_x;
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u32 data_y;
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u32 data_z;
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u32 data_w;
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};
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struct ColorBuffer {
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enum class EndianSwap : u32 {
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None = 0,
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Swap8In16 = 1,
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Swap8In32 = 2,
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Swap8In64 = 3,
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};
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enum class Format : u32 {
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Invalid = 0,
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Color_8 = 1,
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Color_16 = 2,
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Color_8_8 = 3,
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Color_32 = 4,
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Color_16_16 = 5,
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Color_10_11_11 = 6,
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Color_11_11_10 = 7,
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Color_10_10_10_2 = 8,
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Color_2_10_10_10 = 9,
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Color_8_8_8_8 = 10,
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Color_32_32 = 11,
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Color_16_16_16_16 = 12,
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Color_32_32_32_32 = 14,
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Color_5_6_5 = 16,
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Color_1_5_5_5 = 17,
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Color_5_5_5_1 = 18,
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Color_4_4_4_4 = 19,
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Color_8_24 = 20,
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Color_24_8 = 21,
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Color_X24_8_32_FL = 22,
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};
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enum class NumberType : u32 {
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Unorm = 0,
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Snorm = 1,
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Uint = 4,
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Sint = 5,
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Srgb = 6,
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Float = 7,
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};
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enum class SwapMode : u32 {
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Standard = 0,
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Alternate = 1,
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StandardReverse = 2,
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AlternateReverse = 3,
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};
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enum class RoundMode : u32 {
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ByHalf = 0,
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Truncate = 1,
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};
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u32 base_address;
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union {
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BitField<0, 11, u32> tile_max;
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BitField<20, 11, u32> fmask_tile_max;
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} pitch;
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union {
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BitField<0, 22, u32> tile_max;
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} slice;
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union {
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BitField<0, 11, u32> slice_start;
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BitField<13, 11, u32> slice_max;
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} view;
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union {
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BitField<0, 2, EndianSwap> endian;
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BitField<2, 5, Format> format;
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BitField<7, 1, u32> linear_general;
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BitField<8, 2, NumberType> number_type;
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BitField<11, 2, SwapMode> comp_swap;
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BitField<13, 1, u32> fast_clear;
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BitField<14, 1, u32> compression;
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BitField<15, 1, u32> blend_clamp;
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BitField<16, 1, u32> blend_bypass;
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BitField<17, 1, u32> simple_float;
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BitField<18, 1, RoundMode> round_mode;
|
||||
BitField<19, 1, u32> cmask_is_linear;
|
||||
} info;
|
||||
union {
|
||||
BitField<0, 5, u32> tile_mode_index;
|
||||
BitField<5, 5, u32> fmask_tile_mode_index;
|
||||
BitField<12, 3, u32> num_samples_log2;
|
||||
BitField<15, 3, u32> num_fragments_log2;
|
||||
BitField<18, 1, u32> force_dst_alpha_1;
|
||||
} attrib;
|
||||
INSERT_PADDING_WORDS(1);
|
||||
u32 cmask_base_address;
|
||||
union {
|
||||
BitField<0, 14, u32> tile_max;
|
||||
} cmask_slice;
|
||||
u32 fmask_base_address;
|
||||
union {
|
||||
BitField<0, 14, u32> tile_max;
|
||||
} fmask_slice;
|
||||
u32 clear_word0;
|
||||
u32 clear_word1;
|
||||
INSERT_PADDING_WORDS(2);
|
||||
|
||||
u32 Pitch() const {
|
||||
return (pitch.tile_max + 1) << 3;
|
||||
}
|
||||
|
||||
u32 Height() const {
|
||||
return (slice.tile_max + 1) * 64 / Pitch();
|
||||
}
|
||||
|
||||
u64 Address() const {
|
||||
return u64(base_address) << 8;
|
||||
}
|
||||
|
||||
u64 CmaskAddress() const {
|
||||
return u64(cmask_base_address) << 8;
|
||||
}
|
||||
};
|
||||
|
||||
enum class PrimitiveType : u32 {
|
||||
None = 0,
|
||||
PointList = 1,
|
||||
LineList = 2,
|
||||
LineStrip = 3,
|
||||
TriangleList = 4,
|
||||
TriangleFan = 5,
|
||||
TriangleStrip = 6,
|
||||
PatchPrimitive = 9,
|
||||
AdjLineList = 10,
|
||||
AdjLineStrip = 11,
|
||||
AdjTriangleList = 12,
|
||||
AdjTriangleStrip = 13,
|
||||
RectList = 17,
|
||||
LineLoop = 18,
|
||||
QuadList = 19,
|
||||
QuadStrip = 20,
|
||||
Polygon = 21,
|
||||
};
|
||||
|
||||
union Regs {
|
||||
struct {
|
||||
INSERT_PADDING_WORDS(0x2C08);
|
||||
ShaderProgram ps_program;
|
||||
INSERT_PADDING_WORDS(0x2C);
|
||||
ShaderProgram vs_program;
|
||||
INSERT_PADDING_WORDS(0xA008 - 0x2C4C - 16);
|
||||
u32 depth_bounds_min;
|
||||
u32 depth_bounds_max;
|
||||
u32 stencil_clear;
|
||||
u32 depth_clear;
|
||||
Scissor screen_scissor;
|
||||
INSERT_PADDING_WORDS(0xA011 - 0xA00C - 2);
|
||||
StencilInfo stencil_info;
|
||||
u32 z_read_base;
|
||||
u32 stencil_read_base;
|
||||
u32 z_write_base;
|
||||
u32 stencil_write_base;
|
||||
DepthSize depth_size;
|
||||
DepthSlice depth_slice;
|
||||
INSERT_PADDING_WORDS(0xA08E - 0xA018);
|
||||
ColorBufferMask color_target_mask;
|
||||
ColorBufferMask color_shader_mask;
|
||||
INSERT_PADDING_WORDS(0xA094 - 0xA08E - 2);
|
||||
std::array<ViewportScissor, NumViewports> viewport_scissors;
|
||||
std::array<ViewportDepth, NumViewports> viewport_depths;
|
||||
INSERT_PADDING_WORDS(0xA10B - 0xA0D4);
|
||||
StencilControl stencil_control;
|
||||
StencilRefMask stencil_ref_front;
|
||||
StencilRefMask stencil_ref_back;
|
||||
INSERT_PADDING_WORDS(1);
|
||||
std::array<ViewportBounds, NumViewports> viewports;
|
||||
std::array<ClipUserData, NumClipPlanes> clip_user_data;
|
||||
INSERT_PADDING_WORDS(0xA1B1 - 0xA187);
|
||||
VsOutputConfig vs_output_config;
|
||||
INSERT_PADDING_WORDS(0xA1C3 - 0xA1B1 - 1);
|
||||
ShaderPosFormat shader_pos_format;
|
||||
ShaderExportFormat z_export_format;
|
||||
ColorExportFormat color_export_format;
|
||||
INSERT_PADDING_WORDS(0xA1F9 - 0xA1C3 - 3);
|
||||
IndexBufferBase index_base_address;
|
||||
INSERT_PADDING_WORDS(1);
|
||||
u32 draw_initiator;
|
||||
INSERT_PADDING_WORDS(0xA200 - 0xA1F9 - 4);
|
||||
DepthControl depth_control;
|
||||
INSERT_PADDING_WORDS(2);
|
||||
DepthBufferControl depth_buffer_control;
|
||||
ClipperControl clipper_control;
|
||||
PolygonControl polygon_control;
|
||||
ViewportControl viewport_control;
|
||||
VsOutputControl vs_output_control;
|
||||
INSERT_PADDING_WORDS(0xA29E - 0xA207 - 1);
|
||||
u32 max_index_size;
|
||||
IndexBufferType index_buffer_type;
|
||||
INSERT_PADDING_WORDS(0xA2A1 - 0xA29E - 2);
|
||||
u32 enable_primitive_id;
|
||||
INSERT_PADDING_WORDS(0xA318 - 0xA2A1 - 1);
|
||||
ColorBuffer color_buffers[NumColorBuffers];
|
||||
INSERT_PADDING_WORDS(0xC242 - 0xA390);
|
||||
PrimitiveType primitive_type;
|
||||
INSERT_PADDING_WORDS(0xC24C - 0xC243);
|
||||
u32 num_indices;
|
||||
VgtNumInstances num_instances;
|
||||
};
|
||||
std::array<u32, NumRegs> reg_array{};
|
||||
};
|
||||
|
||||
Regs regs{};
|
||||
|
||||
public:
|
||||
Liverpool();
|
||||
|
||||
void ProcessCmdList(u32* cmdbuf, u32 size_in_bytes);
|
||||
};
|
||||
|
||||
static_assert(GFX6_3D_REG_INDEX(ps_program) == 0x2C08);
|
||||
static_assert(GFX6_3D_REG_INDEX(vs_program) == 0x2C48);
|
||||
static_assert(GFX6_3D_REG_INDEX(vs_program.user_data) == 0x2C4C);
|
||||
static_assert(GFX6_3D_REG_INDEX(screen_scissor) == 0xA00C);
|
||||
static_assert(GFX6_3D_REG_INDEX(depth_slice) == 0xA017);
|
||||
static_assert(GFX6_3D_REG_INDEX(color_target_mask) == 0xA08E);
|
||||
static_assert(GFX6_3D_REG_INDEX(color_shader_mask) == 0xA08F);
|
||||
static_assert(GFX6_3D_REG_INDEX(viewport_scissors) == 0xA094);
|
||||
static_assert(GFX6_3D_REG_INDEX(stencil_control) == 0xA10B);
|
||||
static_assert(GFX6_3D_REG_INDEX(viewports) == 0xA10F);
|
||||
static_assert(GFX6_3D_REG_INDEX(clip_user_data) == 0xA16F);
|
||||
static_assert(GFX6_3D_REG_INDEX(vs_output_config) == 0xA1B1);
|
||||
static_assert(GFX6_3D_REG_INDEX(shader_pos_format) == 0xA1C3);
|
||||
static_assert(GFX6_3D_REG_INDEX(z_export_format) == 0xA1C4);
|
||||
static_assert(GFX6_3D_REG_INDEX(color_export_format) == 0xA1C5);
|
||||
static_assert(GFX6_3D_REG_INDEX(index_base_address) == 0xA1F9);
|
||||
static_assert(GFX6_3D_REG_INDEX(draw_initiator) == 0xA1FC);
|
||||
static_assert(GFX6_3D_REG_INDEX(clipper_control) == 0xA204);
|
||||
static_assert(GFX6_3D_REG_INDEX(viewport_control) == 0xA206);
|
||||
static_assert(GFX6_3D_REG_INDEX(vs_output_control) == 0xA207);
|
||||
static_assert(GFX6_3D_REG_INDEX(index_buffer_type) == 0xA29F);
|
||||
static_assert(GFX6_3D_REG_INDEX(enable_primitive_id) == 0xA2A1);
|
||||
static_assert(GFX6_3D_REG_INDEX(color_buffers[0].base_address) == 0xA318);
|
||||
static_assert(GFX6_3D_REG_INDEX(color_buffers[0].pitch) == 0xA319);
|
||||
static_assert(GFX6_3D_REG_INDEX(color_buffers[0].slice) == 0xA31A);
|
||||
static_assert(GFX6_3D_REG_INDEX(color_buffers[7].base_address) == 0xA381);
|
||||
static_assert(GFX6_3D_REG_INDEX(primitive_type) == 0xC242);
|
||||
static_assert(GFX6_3D_REG_INDEX(num_instances) == 0xC24D);
|
||||
|
||||
#undef GFX6_3D_REG_INDEX
|
||||
|
||||
} // namespace AmdGpu
|
Loading…
Add table
Add a link
Reference in a new issue