Mirrors/shadPS4
1
0
Fork 0
mirror of https://github.com/shadps4-emu/shadPS4.git synced 2025-06-10 20:53:15 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

video_core: Bloodborne stabilization pt1 (#543)

Browse source 
* shader_recompiler: Writelane elimination pass + null image fix

* spirv: Implement image derivatives

* texture_cache: Reduce page bit size

* clang format

* slot_vector: Back to debug assert

* vk_graphics_pipeline: Handle null tsharp

* spirv: Revert some change

* vk_instance: Support primitive restart on list topology

* page_manager: Adjust windows exception handler

* clang format

* Remove subres tracking

* Will be done separately
This commit is contained in:
TheTurtle 2024-08-24 22:51:47 +03:00 • committed by GitHub
parent 9e4fc17e6c
commit c79b10edc1
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
25 changed files with 187 additions and 107 deletions
Download patch file Download diff file Expand all files Collapse all files

7
src/video_core/texture_cache/image_info.cpp
View file

@ -219,7 +219,12 @@ ImageInfo::ImageInfo(const AmdGpu::Image& image) noexcept {
guest_address = image.Address();
mips_layout.reserve(resources.levels);
tiling_idx = image.tiling_index;
UpdateSize();
}
void ImageInfo::UpdateSize() {
mips_layout.clear();
MipInfo mip_info{};
guest_size_bytes = 0;
for (auto mip = 0u; mip < resources.levels; ++mip) {
@ -265,7 +270,7 @@ ImageInfo::ImageInfo(const AmdGpu::Image& image) noexcept {
ASSERT(!props.is_block);
ASSERT(num_samples == 1);
std::tie(mip_info.pitch, mip_info.size) =
ImageSizeMacroTiled(mip_w, mip_h, bpp, num_samples, image.tiling_index);
ImageSizeMacroTiled(mip_w, mip_h, bpp, num_samples, tiling_idx);
break;
}
default: {

3
src/video_core/texture_cache/image_info.h
View file

@ -29,6 +29,8 @@ struct ImageInfo {
bool IsPacked() const;
bool IsDepthStencil() const;
void UpdateSize();
struct {
VAddr cmask_addr;
VAddr fmask_addr;
@ -69,6 +71,7 @@ struct ImageInfo {
boost::container::small_vector<MipInfo, 14> mips_layout;
VAddr guest_address{0};
u32 guest_size_bytes{0};
u32 tiling_idx{0}; // TODO: merge with existing!
};
} // namespace VideoCore

6
src/video_core/texture_cache/texture_cache.cpp
View file

@ -18,11 +18,15 @@ TextureCache::TextureCache(const Vulkan::Instance& instance_, Vulkan::Scheduler&
BufferCache& buffer_cache_, PageManager& tracker_)
: instance{instance_}, scheduler{scheduler_}, buffer_cache{buffer_cache_}, tracker{tracker_},
tile_manager{instance, scheduler} {
ImageInfo info;
ImageInfo info{};
info.pixel_format = vk::Format::eR8G8B8A8Unorm;
info.type = vk::ImageType::e2D;
info.tiling_idx = u32(AmdGpu::TilingMode::Texture_MicroTiled);
info.num_bits = 32;
info.UpdateSize();
const ImageId null_id = slot_images.insert(instance, scheduler, info);
ASSERT(null_id.index == 0);
slot_images[null_id].flags = ImageFlagBits{};
ImageViewInfo view_info;
void(slot_image_views.insert(instance, view_info, slot_images[null_id], null_id));

2
src/video_core/texture_cache/texture_cache.h
View file

@ -28,7 +28,7 @@ class TextureCache {
using Entry = boost::container::small_vector<ImageId, 16>;
static constexpr size_t AddressSpaceBits = 39;
static constexpr size_t FirstLevelBits = 9;
static constexpr size_t PageBits = 22;
static constexpr size_t PageBits = 20;
};
using PageTable = MultiLevelPageTable<Traits>;