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https://github.com/shadps4-emu/shadPS4.git
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shader_recompiler: Various fixes to shared memory and atomics. (#3075)
* shader_recompiler: Various fixes to shared memory and atomics. * shader_recompiler: Re-type non-32bit load/stores.
This commit is contained in:
squidbus
GitHub
parent
b49340dff8
commit
ca92e72efe
17 changed files with 391 additions and 227 deletions
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@ -27,6 +27,19 @@ Id SharedAtomicU32(EmitContext& ctx, Id offset, Id value,
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});
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}
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Id SharedAtomicU32IncDec(EmitContext& ctx, Id offset,
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Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id)) {
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const Id shift_id{ctx.ConstU32(2U)};
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const Id index{ctx.OpShiftRightLogical(ctx.U32[1], offset, shift_id)};
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const u32 num_elements{Common::DivCeil(ctx.runtime_info.cs_info.shared_memory_size, 4u)};
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const Id pointer{
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ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, ctx.u32_zero_value, index)};
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const auto [scope, semantics]{AtomicArgs(ctx)};
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return AccessBoundsCheck<32>(ctx, index, ctx.ConstU32(num_elements), [&] {
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return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics);
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});
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}
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Id SharedAtomicU64(EmitContext& ctx, Id offset, Id value,
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Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) {
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const Id shift_id{ctx.ConstU32(3U)};
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@ -40,19 +53,6 @@ Id SharedAtomicU64(EmitContext& ctx, Id offset, Id value,
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});
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}
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Id SharedAtomicU32_IncDec(EmitContext& ctx, Id offset,
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Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id)) {
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const Id shift_id{ctx.ConstU32(2U)};
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const Id index{ctx.OpShiftRightLogical(ctx.U32[1], offset, shift_id)};
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const u32 num_elements{Common::DivCeil(ctx.runtime_info.cs_info.shared_memory_size, 4u)};
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const Id pointer{
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ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, ctx.u32_zero_value, index)};
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const auto [scope, semantics]{AtomicArgs(ctx)};
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return AccessBoundsCheck<32>(ctx, index, ctx.ConstU32(num_elements), [&] {
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return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics);
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});
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}
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Id BufferAtomicU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value,
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Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) {
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const auto& buffer = ctx.buffers[handle];
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@ -68,6 +68,21 @@ Id BufferAtomicU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id
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});
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}
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Id BufferAtomicU32IncDec(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address,
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Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id)) {
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const auto& buffer = ctx.buffers[handle];
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if (Sirit::ValidId(buffer.offset)) {
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address = ctx.OpIAdd(ctx.U32[1], address, buffer.offset);
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}
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const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(2u));
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const auto [id, pointer_type] = buffer[EmitContext::PointerType::U32];
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const Id ptr = ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, index);
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const auto [scope, semantics]{AtomicArgs(ctx)};
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return AccessBoundsCheck<32>(ctx, index, buffer.size_dwords, [&] {
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return (ctx.*atomic_func)(ctx.U32[1], ptr, scope, semantics);
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});
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}
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Id BufferAtomicU32CmpSwap(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value,
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Id cmp_value,
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Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id, Id, Id)) {
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@ -156,12 +171,12 @@ Id EmitSharedAtomicISub32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicISub);
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}
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Id EmitSharedAtomicIIncrement32(EmitContext& ctx, Id offset) {
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return SharedAtomicU32_IncDec(ctx, offset, &Sirit::Module::OpAtomicIIncrement);
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Id EmitSharedAtomicInc32(EmitContext& ctx, Id offset) {
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return SharedAtomicU32IncDec(ctx, offset, &Sirit::Module::OpAtomicIIncrement);
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}
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Id EmitSharedAtomicIDecrement32(EmitContext& ctx, Id offset) {
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return SharedAtomicU32_IncDec(ctx, offset, &Sirit::Module::OpAtomicIDecrement);
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Id EmitSharedAtomicDec32(EmitContext& ctx, Id offset) {
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return SharedAtomicU32IncDec(ctx, offset, &Sirit::Module::OpAtomicIDecrement);
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}
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Id EmitBufferAtomicIAdd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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@ -172,6 +187,10 @@ Id EmitBufferAtomicIAdd64(EmitContext& ctx, IR::Inst* inst, u32 handle, Id addre
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return BufferAtomicU64(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicIAdd);
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}
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Id EmitBufferAtomicISub32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicISub);
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}
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Id EmitBufferAtomicSMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicSMin);
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}
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@ -188,14 +207,12 @@ Id EmitBufferAtomicUMax32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id addre
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return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicUMax);
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}
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Id EmitBufferAtomicInc32(EmitContext&, IR::Inst*, u32, Id, Id) {
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// TODO
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UNREACHABLE_MSG("Unsupported BUFFER_ATOMIC opcode: ", IR::Opcode::BufferAtomicInc32);
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Id EmitBufferAtomicInc32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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return BufferAtomicU32IncDec(ctx, inst, handle, address, &Sirit::Module::OpAtomicIIncrement);
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}
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Id EmitBufferAtomicDec32(EmitContext&, IR::Inst*, u32, Id, Id) {
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// TODO
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UNREACHABLE_MSG("Unsupported BUFFER_ATOMIC opcode: ", IR::Opcode::BufferAtomicDec32);
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Id EmitBufferAtomicDec32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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return BufferAtomicU32IncDec(ctx, inst, handle, address, &Sirit::Module::OpAtomicIDecrement);
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}
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Id EmitBufferAtomicAnd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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@ -1,31 +1,54 @@
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// SPDX-FileCopyrightText: Copyright 2025 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
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#pragma once
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#include "shader_recompiler/backend/spirv/spirv_emit_context.h"
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namespace Shader::Backend::SPIRV {
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template <u32 bit_size>
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auto AccessBoundsCheck(EmitContext& ctx, Id index, Id buffer_size, auto emit_func) {
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Id zero_value{};
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template <u32 bit_size, u32 num_components = 1, bool is_float = false>
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std::tuple<Id, Id> ResolveTypeAndZero(EmitContext& ctx) {
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Id result_type{};
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if constexpr (bit_size == 64) {
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zero_value = ctx.u64_zero_value;
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Id zero_value{};
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if constexpr (bit_size == 64 && num_components == 1 && !is_float) {
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result_type = ctx.U64;
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zero_value = ctx.u64_zero_value;
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} else if constexpr (bit_size == 32) {
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zero_value = ctx.u32_zero_value;
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result_type = ctx.U32[1];
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} else if constexpr (bit_size == 16) {
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zero_value = ctx.u16_zero_value;
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if (is_float) {
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result_type = ctx.F32[num_components];
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zero_value = ctx.f32_zero_value;
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} else {
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result_type = ctx.U32[num_components];
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zero_value = ctx.u32_zero_value;
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}
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} else if constexpr (bit_size == 16 && num_components == 1 && !is_float) {
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result_type = ctx.U16;
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zero_value = ctx.u16_zero_value;
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} else if constexpr (bit_size == 8 && num_components == 1 && !is_float) {
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result_type = ctx.U8;
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zero_value = ctx.u8_zero_value;
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} else {
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static_assert(false, "type not supported");
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static_assert(false, "Type not supported.");
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}
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if (num_components > 1) {
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std::array<Id, num_components> zero_ids;
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zero_ids.fill(zero_value);
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zero_value = ctx.ConstantComposite(result_type, zero_ids);
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}
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return {result_type, zero_value};
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}
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template <u32 bit_size, u32 num_components = 1, bool is_float = false>
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auto AccessBoundsCheck(EmitContext& ctx, Id index, Id buffer_size, auto emit_func) {
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if (Sirit::ValidId(buffer_size)) {
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// Bounds checking enabled, wrap in a conditional branch to make sure that
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// the atomic is not mistakenly executed when the index is out of bounds.
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const Id in_bounds = ctx.OpULessThan(ctx.U1[1], index, buffer_size);
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auto compare_index = index;
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if (num_components > 1) {
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compare_index = ctx.OpIAdd(ctx.U32[1], index, ctx.ConstU32(num_components - 1));
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}
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const Id in_bounds = ctx.OpULessThan(ctx.U1[1], compare_index, buffer_size);
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const Id ib_label = ctx.OpLabel();
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const Id end_label = ctx.OpLabel();
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ctx.OpSelectionMerge(end_label, spv::SelectionControlMask::MaskNone);
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@ -36,6 +59,8 @@ auto AccessBoundsCheck(EmitContext& ctx, Id index, Id buffer_size, auto emit_fun
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ctx.OpBranch(end_label);
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ctx.AddLabel(end_label);
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if (Sirit::ValidId(ib_result)) {
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const auto [result_type, zero_value] =
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ResolveTypeAndZero<bit_size, num_components, is_float>(ctx);
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return ctx.OpPhi(result_type, ib_result, ib_label, zero_value, last_label);
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} else {
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return Id{0};
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@ -45,4 +70,21 @@ auto AccessBoundsCheck(EmitContext& ctx, Id index, Id buffer_size, auto emit_fun
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return emit_func();
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}
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template <u32 bit_size, u32 num_components = 1, bool is_float = false>
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static Id LoadAccessBoundsCheck(EmitContext& ctx, Id index, Id buffer_size, Id result) {
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if (Sirit::ValidId(buffer_size)) {
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// Bounds checking enabled, wrap in a select.
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auto compare_index = index;
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if (num_components > 1) {
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compare_index = ctx.OpIAdd(ctx.U32[1], index, ctx.ConstU32(num_components - 1));
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}
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const Id in_bounds = ctx.OpULessThan(ctx.U1[1], compare_index, buffer_size);
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const auto [result_type, zero_value] =
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ResolveTypeAndZero<bit_size, num_components, is_float>(ctx);
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return ctx.OpSelect(result_type, in_bounds, result, zero_value);
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}
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// Bounds checking not enabled, just return the plain value.
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return result;
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}
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} // namespace Shader::Backend::SPIRV
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@ -11,6 +11,8 @@
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#include <magic_enum/magic_enum.hpp>
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#include "emit_spirv_bounds.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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@ -239,8 +241,8 @@ Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, u32 comp, Id index) {
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}
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if (IR::IsParam(attr)) {
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const u32 index{u32(attr) - u32(IR::Attribute::Param0)};
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const auto& param{ctx.input_params.at(index)};
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const u32 param_index{u32(attr) - u32(IR::Attribute::Param0)};
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const auto& param{ctx.input_params.at(param_index)};
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if (param.buffer_handle >= 0) {
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const auto step_rate = EmitReadStepRate(ctx, param.id.value);
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const auto offset = ctx.OpIAdd(
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@ -415,27 +417,6 @@ void EmitSetPatch(EmitContext& ctx, IR::Patch patch, Id value) {
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ctx.OpStore(pointer, value);
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}
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template <u32 N>
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static Id EmitLoadBufferBoundsCheck(EmitContext& ctx, Id index, Id buffer_size, Id result,
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bool is_float) {
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if (Sirit::ValidId(buffer_size)) {
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// Bounds checking enabled, wrap in a select.
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const auto result_type = is_float ? ctx.F32[N] : ctx.U32[N];
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auto compare_index = index;
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auto zero_value = is_float ? ctx.f32_zero_value : ctx.u32_zero_value;
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if (N > 1) {
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compare_index = ctx.OpIAdd(ctx.U32[1], index, ctx.ConstU32(N - 1));
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std::array<Id, N> zero_ids;
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zero_ids.fill(zero_value);
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zero_value = ctx.ConstantComposite(result_type, zero_ids);
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}
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const Id in_bounds = ctx.OpULessThan(ctx.U1[1], compare_index, buffer_size);
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return ctx.OpSelect(result_type, in_bounds, result, zero_value);
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}
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// Bounds checking not enabled, just return the plain value.
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return result;
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}
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template <u32 N, PointerType alias>
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static Id EmitLoadBufferB32xN(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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const auto flags = inst->Flags<IR::BufferInstInfo>();
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@ -454,8 +435,9 @@ static Id EmitLoadBufferB32xN(EmitContext& ctx, IR::Inst* inst, u32 handle, Id a
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const Id result_i = ctx.OpLoad(data_types[1], ptr_i);
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if (!flags.typed) {
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// Untyped loads have bounds checking per-component.
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ids.push_back(EmitLoadBufferBoundsCheck<1>(ctx, index_i, spv_buffer.size_dwords,
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result_i, alias == PointerType::F32));
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ids.push_back(LoadAccessBoundsCheck < 32, 1,
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alias ==
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PointerType::F32 > (ctx, index_i, spv_buffer.size_dwords, result_i));
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} else {
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ids.push_back(result_i);
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}
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@ -464,8 +446,8 @@ static Id EmitLoadBufferB32xN(EmitContext& ctx, IR::Inst* inst, u32 handle, Id a
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const Id result = N == 1 ? ids[0] : ctx.OpCompositeConstruct(data_types[N], ids);
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if (flags.typed) {
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// Typed loads have single bounds check for the whole load.
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return EmitLoadBufferBoundsCheck<N>(ctx, index, spv_buffer.size_dwords, result,
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alias == PointerType::F32);
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return LoadAccessBoundsCheck < 32, N,
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alias == PointerType::F32 > (ctx, index, spv_buffer.size_dwords, result);
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}
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return result;
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}
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@ -477,8 +459,8 @@ Id EmitLoadBufferU8(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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}
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const auto [id, pointer_type] = spv_buffer[PointerType::U8];
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const Id ptr{ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, address)};
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const Id result{ctx.OpUConvert(ctx.U32[1], ctx.OpLoad(ctx.U8, ptr))};
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return EmitLoadBufferBoundsCheck<1>(ctx, address, spv_buffer.size, result, false);
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const Id result{ctx.OpLoad(ctx.U8, ptr)};
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return LoadAccessBoundsCheck<8>(ctx, address, spv_buffer.size, result);
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}
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Id EmitLoadBufferU16(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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@ -489,8 +471,8 @@ Id EmitLoadBufferU16(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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const auto [id, pointer_type] = spv_buffer[PointerType::U16];
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const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(1u));
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const Id ptr{ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, index)};
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const Id result{ctx.OpUConvert(ctx.U32[1], ctx.OpLoad(ctx.U16, ptr))};
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return EmitLoadBufferBoundsCheck<1>(ctx, index, spv_buffer.size_shorts, result, false);
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const Id result{ctx.OpLoad(ctx.U16, ptr)};
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return LoadAccessBoundsCheck<16>(ctx, index, spv_buffer.size_shorts, result);
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}
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Id EmitLoadBufferU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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@ -509,6 +491,18 @@ Id EmitLoadBufferU32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address)
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return EmitLoadBufferB32xN<4, PointerType::U32>(ctx, inst, handle, address);
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}
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Id EmitLoadBufferU64(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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const auto& spv_buffer = ctx.buffers[handle];
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if (Sirit::ValidId(spv_buffer.offset)) {
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address = ctx.OpIAdd(ctx.U32[1], address, spv_buffer.offset);
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}
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const auto [id, pointer_type] = spv_buffer[PointerType::U64];
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const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(3u));
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const Id ptr{ctx.OpAccessChain(pointer_type, id, ctx.u64_zero_value, index)};
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const Id result{ctx.OpLoad(ctx.U64, ptr)};
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return LoadAccessBoundsCheck<64>(ctx, index, spv_buffer.size_qwords, result);
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}
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Id EmitLoadBufferF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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return EmitLoadBufferB32xN<1, PointerType::F32>(ctx, inst, handle, address);
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}
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@ -529,29 +523,6 @@ Id EmitLoadBufferFormatF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id addr
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UNREACHABLE_MSG("SPIR-V instruction");
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}
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template <u32 N>
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void EmitStoreBufferBoundsCheck(EmitContext& ctx, Id index, Id buffer_size, auto emit_func) {
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if (Sirit::ValidId(buffer_size)) {
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// Bounds checking enabled, wrap in a conditional branch.
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auto compare_index = index;
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if (N > 1) {
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compare_index = ctx.OpIAdd(ctx.U32[1], index, ctx.ConstU32(N - 1));
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}
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const Id in_bounds = ctx.OpULessThan(ctx.U1[1], compare_index, buffer_size);
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const Id in_bounds_label = ctx.OpLabel();
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const Id merge_label = ctx.OpLabel();
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ctx.OpSelectionMerge(merge_label, spv::SelectionControlMask::MaskNone);
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ctx.OpBranchConditional(in_bounds, in_bounds_label, merge_label);
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ctx.AddLabel(in_bounds_label);
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emit_func();
|
||||
ctx.OpBranch(merge_label);
|
||||
ctx.AddLabel(merge_label);
|
||||
return;
|
||||
}
|
||||
// Bounds checking not enabled, just perform the store.
|
||||
emit_func();
|
||||
}
|
||||
|
||||
template <u32 N, PointerType alias>
|
||||
static void EmitStoreBufferB32xN(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address,
|
||||
Id value) {
|
||||
|
|
@ -569,19 +540,25 @@ static void EmitStoreBufferB32xN(EmitContext& ctx, IR::Inst* inst, u32 handle, I
|
|||
const Id index_i = i == 0 ? index : ctx.OpIAdd(ctx.U32[1], index, ctx.ConstU32(i));
|
||||
const Id ptr_i = ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, index_i);
|
||||
const Id value_i = N == 1 ? value : ctx.OpCompositeExtract(data_types[1], value, i);
|
||||
auto store_i = [&]() { ctx.OpStore(ptr_i, value_i); };
|
||||
auto store_i = [&] {
|
||||
ctx.OpStore(ptr_i, value_i);
|
||||
return Id{};
|
||||
};
|
||||
if (!flags.typed) {
|
||||
// Untyped stores have bounds checking per-component.
|
||||
EmitStoreBufferBoundsCheck<1>(ctx, index_i, spv_buffer.size_dwords, store_i);
|
||||
AccessBoundsCheck<32, 1, alias == PointerType::F32>(
|
||||
ctx, index_i, spv_buffer.size_dwords, store_i);
|
||||
} else {
|
||||
store_i();
|
||||
}
|
||||
}
|
||||
return Id{};
|
||||
};
|
||||
|
||||
if (flags.typed) {
|
||||
// Typed stores have single bounds check for the whole store.
|
||||
EmitStoreBufferBoundsCheck<N>(ctx, index, spv_buffer.size_dwords, store);
|
||||
AccessBoundsCheck<32, N, alias == PointerType::F32>(ctx, index, spv_buffer.size_dwords,
|
||||
store);
|
||||
} else {
|
||||
store();
|
||||
}
|
||||
|
|
@ -594,8 +571,10 @@ void EmitStoreBufferU8(EmitContext& ctx, IR::Inst*, u32 handle, Id address, Id v
|
|||
}
|
||||
const auto [id, pointer_type] = spv_buffer[PointerType::U8];
|
||||
const Id ptr{ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, address)};
|
||||
const Id result{ctx.OpUConvert(ctx.U8, value)};
|
||||
EmitStoreBufferBoundsCheck<1>(ctx, address, spv_buffer.size, [&] { ctx.OpStore(ptr, result); });
|
||||
AccessBoundsCheck<8>(ctx, address, spv_buffer.size, [&] {
|
||||
ctx.OpStore(ptr, value);
|
||||
return Id{};
|
||||
});
|
||||
}
|
||||
|
||||
void EmitStoreBufferU16(EmitContext& ctx, IR::Inst*, u32 handle, Id address, Id value) {
|
||||
|
|
@ -606,9 +585,10 @@ void EmitStoreBufferU16(EmitContext& ctx, IR::Inst*, u32 handle, Id address, Id
|
|||
const auto [id, pointer_type] = spv_buffer[PointerType::U16];
|
||||
const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(1u));
|
||||
const Id ptr{ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, index)};
|
||||
const Id result{ctx.OpUConvert(ctx.U16, value)};
|
||||
EmitStoreBufferBoundsCheck<1>(ctx, index, spv_buffer.size_shorts,
|
||||
[&] { ctx.OpStore(ptr, result); });
|
||||
AccessBoundsCheck<16>(ctx, index, spv_buffer.size_shorts, [&] {
|
||||
ctx.OpStore(ptr, value);
|
||||
return Id{};
|
||||
});
|
||||
}
|
||||
|
||||
void EmitStoreBufferU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
|
||||
|
|
@ -627,6 +607,20 @@ void EmitStoreBufferU32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id addre
|
|||
EmitStoreBufferB32xN<4, PointerType::U32>(ctx, inst, handle, address, value);
|
||||
}
|
||||
|
||||
void EmitStoreBufferU64(EmitContext& ctx, IR::Inst*, u32 handle, Id address, Id value) {
|
||||
const auto& spv_buffer = ctx.buffers[handle];
|
||||
if (Sirit::ValidId(spv_buffer.offset)) {
|
||||
address = ctx.OpIAdd(ctx.U32[1], address, spv_buffer.offset);
|
||||
}
|
||||
const auto [id, pointer_type] = spv_buffer[PointerType::U64];
|
||||
const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(3u));
|
||||
const Id ptr{ctx.OpAccessChain(pointer_type, id, ctx.u64_zero_value, index)};
|
||||
AccessBoundsCheck<64>(ctx, index, spv_buffer.size_qwords, [&] {
|
||||
ctx.OpStore(ptr, value);
|
||||
return Id{};
|
||||
});
|
||||
}
|
||||
|
||||
void EmitStoreBufferF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
|
||||
EmitStoreBufferB32xN<1, PointerType::F32>(ctx, inst, handle, address, value);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -263,4 +263,12 @@ Id EmitConvertU32U16(EmitContext& ctx, Id value) {
|
|||
return ctx.OpUConvert(ctx.U32[1], value);
|
||||
}
|
||||
|
||||
Id EmitConvertU8U32(EmitContext& ctx, Id value) {
|
||||
return ctx.OpUConvert(ctx.U8, value);
|
||||
}
|
||||
|
||||
Id EmitConvertU32U8(EmitContext& ctx, Id value) {
|
||||
return ctx.OpUConvert(ctx.U32[1], value);
|
||||
}
|
||||
|
||||
} // namespace Shader::Backend::SPIRV
|
||||
|
|
|
|||
|
|
@ -69,6 +69,7 @@ Id EmitLoadBufferU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
|
|||
Id EmitLoadBufferU32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
|
||||
Id EmitLoadBufferU32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
|
||||
Id EmitLoadBufferU32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
|
||||
Id EmitLoadBufferU64(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
|
||||
Id EmitLoadBufferF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
|
||||
Id EmitLoadBufferF32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
|
||||
Id EmitLoadBufferF32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
|
||||
|
|
@ -80,6 +81,7 @@ void EmitStoreBufferU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address
|
|||
void EmitStoreBufferU32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
void EmitStoreBufferU32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
void EmitStoreBufferU32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
void EmitStoreBufferU64(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
void EmitStoreBufferF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
void EmitStoreBufferF32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
void EmitStoreBufferF32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
|
|
@ -87,12 +89,13 @@ void EmitStoreBufferF32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id addre
|
|||
void EmitStoreBufferFormatF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
Id EmitBufferAtomicIAdd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
Id EmitBufferAtomicIAdd64(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
Id EmitBufferAtomicISub32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
Id EmitBufferAtomicSMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
Id EmitBufferAtomicUMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
Id EmitBufferAtomicSMax32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
Id EmitBufferAtomicUMax32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
Id EmitBufferAtomicInc32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
Id EmitBufferAtomicDec32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
Id EmitBufferAtomicInc32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
|
||||
Id EmitBufferAtomicDec32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
|
||||
Id EmitBufferAtomicAnd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
Id EmitBufferAtomicOr32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
Id EmitBufferAtomicXor32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
|
||||
|
|
@ -136,8 +139,8 @@ Id EmitSharedAtomicSMin32(EmitContext& ctx, Id offset, Id value);
|
|||
Id EmitSharedAtomicAnd32(EmitContext& ctx, Id offset, Id value);
|
||||
Id EmitSharedAtomicOr32(EmitContext& ctx, Id offset, Id value);
|
||||
Id EmitSharedAtomicXor32(EmitContext& ctx, Id offset, Id value);
|
||||
Id EmitSharedAtomicIIncrement32(EmitContext& ctx, Id offset);
|
||||
Id EmitSharedAtomicIDecrement32(EmitContext& ctx, Id offset);
|
||||
Id EmitSharedAtomicInc32(EmitContext& ctx, Id offset);
|
||||
Id EmitSharedAtomicDec32(EmitContext& ctx, Id offset);
|
||||
Id EmitSharedAtomicISub32(EmitContext& ctx, Id offset, Id value);
|
||||
|
||||
Id EmitCompositeConstructU32x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2);
|
||||
|
|
@ -461,6 +464,8 @@ Id EmitConvertF64U32(EmitContext& ctx, Id value);
|
|||
Id EmitConvertF64U64(EmitContext& ctx, Id value);
|
||||
Id EmitConvertU16U32(EmitContext& ctx, Id value);
|
||||
Id EmitConvertU32U16(EmitContext& ctx, Id value);
|
||||
Id EmitConvertU8U32(EmitContext& ctx, Id value);
|
||||
Id EmitConvertU32U8(EmitContext& ctx, Id value);
|
||||
|
||||
Id EmitImageSampleRaw(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address1, Id address2,
|
||||
Id address3, Id address4);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue