mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-17 17:05:02 +00:00
recompiler: trivial missing ops (VALU OR and SALU LE, GE) added
This commit is contained in:
parent
7fcb758da2
commit
cb2cf7d93c
3 changed files with 17 additions and 0 deletions
|
@ -228,6 +228,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
|
|||
case Opcode::V_AND_B32:
|
||||
translator.V_AND_B32(inst);
|
||||
break;
|
||||
case Opcode::V_OR_B32:
|
||||
translator.V_OR_B32(inst);
|
||||
break;
|
||||
case Opcode::V_LSHLREV_B32:
|
||||
translator.V_LSHLREV_B32(inst);
|
||||
break;
|
||||
|
@ -318,6 +321,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
|
|||
case Opcode::V_CMP_EQ_I32:
|
||||
translator.V_CMP_U32(ConditionOp::EQ, true, false, inst);
|
||||
break;
|
||||
case Opcode::V_CMP_LE_I32:
|
||||
translator.V_CMP_U32(ConditionOp::LE, true, false, inst);
|
||||
break;
|
||||
case Opcode::V_CMP_NE_U32:
|
||||
translator.V_CMP_U32(ConditionOp::LG, false, false, inst);
|
||||
break;
|
||||
|
@ -378,6 +384,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
|
|||
case Opcode::S_CMP_GT_I32:
|
||||
translator.S_CMP(ConditionOp::GT, true, inst);
|
||||
break;
|
||||
case Opcode::S_CMP_GE_I32:
|
||||
translator.S_CMP(ConditionOp::GE, true, inst);
|
||||
break;
|
||||
case Opcode::S_CMP_EQ_I32:
|
||||
translator.S_CMP(ConditionOp::EQ, true, inst);
|
||||
break;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue