mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-30 23:33:17 +00:00
Initial instancing and asynchronous compute queues (#207)
* gnm_driver: added `sceGnmRegisterOwner` and `sceGnmRegisterResource` * video_out: `sceVideoOutGetDeviceCapabilityInfo` for sdk runtime * gnm_driver: correct vqid index range * amdgpu: indirect buffer, release mem and some additional irq modes * amdgpu: added ASC commands processor * shader_recompiler: added support for fetch instance id * amdgpu: classic bitfields for T# representation (debugging experience) * renderer_vulkan: skip zero sized VBs from binding * texture_cache: image upload logic moved into `Image` object * gnm_driver: `sceGnmDingDong` implementation * texture_cache: `Image` usage flags moved; correct VO buffer pitch
This commit is contained in:
psucien
GitHub
parent
a9cbd8287c
commit
cb6b21de1f
19 changed files with 361 additions and 100 deletions
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@ -12,7 +12,7 @@ namespace AmdGpu {
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static const char* dcb_task_name{"DCB_TASK"};
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static const char* ccb_task_name{"CCB_TASK"};
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static const char* asc_task_name{"ACB_TASK"};
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static const char* acb_task_name{"ACB_TASK"};
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std::array<u8, 48_KB> Liverpool::ConstantEngine::constants_heap;
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@ -381,6 +381,8 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
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}
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Liverpool::Task Liverpool::ProcessCompute(std::span<const u32> acb) {
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TracyFiberEnter(acb_task_name);
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while (!acb.empty()) {
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const auto* header = reinterpret_cast<const PM4Header*>(acb.data());
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const u32 type = header->type;
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@ -393,6 +395,69 @@ Liverpool::Task Liverpool::ProcessCompute(std::span<const u32> acb) {
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const PM4ItOpcode opcode = header->type3.opcode;
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const auto* it_body = reinterpret_cast<const u32*>(header) + 1;
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switch (opcode) {
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case PM4ItOpcode::Nop: {
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const auto* nop = reinterpret_cast<const PM4CmdNop*>(header);
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break;
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}
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case PM4ItOpcode::IndirectBuffer: {
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const auto* indirect_buffer = reinterpret_cast<const PM4CmdIndirectBuffer*>(header);
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auto task =
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ProcessCompute({indirect_buffer->Address<const u32>(), indirect_buffer->ib_size});
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while (!task.handle.done()) {
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task.handle.resume();
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TracyFiberLeave;
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co_yield {};
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TracyFiberEnter(acb_task_name);
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};
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break;
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}
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case PM4ItOpcode::AcquireMem: {
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break;
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}
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case PM4ItOpcode::SetShReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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std::memcpy(®s.reg_array[ShRegWordOffset + set_data->reg_offset], header + 2,
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(count - 1) * sizeof(u32));
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break;
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}
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case PM4ItOpcode::DispatchDirect: {
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const auto* dispatch_direct = reinterpret_cast<const PM4CmdDispatchDirect*>(header);
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regs.cs_program.dim_x = dispatch_direct->dim_x;
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regs.cs_program.dim_y = dispatch_direct->dim_y;
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regs.cs_program.dim_z = dispatch_direct->dim_z;
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regs.cs_program.dispatch_initiator = dispatch_direct->dispatch_initiator;
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if (rasterizer && (regs.cs_program.dispatch_initiator & 1)) {
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rasterizer->DispatchDirect();
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}
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break;
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}
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case PM4ItOpcode::WriteData: {
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const auto* write_data = reinterpret_cast<const PM4CmdWriteData*>(header);
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ASSERT(write_data->dst_sel.Value() == 2 || write_data->dst_sel.Value() == 5);
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const u32 data_size = (header->type3.count.Value() - 2) * 4;
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if (!write_data->wr_one_addr.Value()) {
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std::memcpy(write_data->Address<void*>(), write_data->data, data_size);
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} else {
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UNREACHABLE();
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}
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break;
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}
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case PM4ItOpcode::WaitRegMem: {
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const auto* wait_reg_mem = reinterpret_cast<const PM4CmdWaitRegMem*>(header);
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ASSERT(wait_reg_mem->engine.Value() == PM4CmdWaitRegMem::Engine::Me);
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while (!wait_reg_mem->Test()) {
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TracyFiberLeave;
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co_yield {};
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TracyFiberEnter(acb_task_name);
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}
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break;
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}
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case PM4ItOpcode::ReleaseMem: {
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const auto* release_mem = reinterpret_cast<const PM4CmdReleaseMem*>(header);
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release_mem->SignalFence(Platform::InterruptId::Compute0RelMem); // <---
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break;
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}
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default:
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UNREACHABLE_MSG("Unknown PM4 type 3 opcode {:#x} with count {}",
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static_cast<u32>(opcode), count);
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@ -401,7 +466,7 @@ Liverpool::Task Liverpool::ProcessCompute(std::span<const u32> acb) {
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acb = acb.subspan(header->type3.NumWords() + 1);
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}
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return {}; // Not a coroutine yet
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TracyFiberLeave;
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}
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void Liverpool::SubmitGfx(std::span<const u32> dcb, std::span<const u32> ccb) {
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@ -265,6 +265,7 @@ enum class InterruptSelect : u32 {
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None = 0,
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IrqOnly = 1,
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IrqWhenWriteConfirm = 2,
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IrqUndocumented = 3,
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};
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struct PM4CmdEventWriteEop {
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@ -299,6 +300,9 @@ struct PM4CmdEventWriteEop {
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void SignalFence() const {
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switch (data_sel.Value()) {
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case DataSelect::None: {
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break;
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}
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case DataSelect::Data32Low: {
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*Address<u32>() = DataDWord();
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break;
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@ -321,6 +325,9 @@ struct PM4CmdEventWriteEop {
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// No interrupt
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break;
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}
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case InterruptSelect::IrqOnly:
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ASSERT(data_sel == DataSelect::None);
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[[fallthrough]];
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case InterruptSelect::IrqWhenWriteConfirm: {
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Platform::IrqC::Instance()->Signal(Platform::InterruptId::GfxEop);
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break;
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@ -559,4 +566,105 @@ struct PM4CmdDrawIndexBase {
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u32 addr_hi;
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};
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struct PM4CmdIndirectBuffer {
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PM4Type3Header header;
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u32 ibase_lo; ///< Indirect buffer base address, must be 4 byte aligned
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union {
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BitField<0, 16, u32> ibase_hi; ///< Indirect buffer base address
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u32 dw1;
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};
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union {
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BitField<0, 20, u32> ib_size; ///< Indirect buffer size
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BitField<20, 1, u32> chain; ///< set to chain to IB allocations
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BitField<24, 8, u32> vmid; ///< Virtual memory domain ID for command buffer
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u32 dw2;
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};
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template <typename T>
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T* Address() const {
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return reinterpret_cast<T*>((u64(ibase_hi) << 32u) | ibase_lo);
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}
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};
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struct PM4CmdReleaseMem {
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PM4Type3Header header;
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union {
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BitField<0, 6, u32> event_type; ///< Event type written to VGT_EVENT_INITIATOR
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BitField<8, 4, u32> event_index; ///< Event index
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BitField<12, 1, u32> tcl1_vol_action_ena;
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BitField<13, 1, u32> tc_vol_action_ena;
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BitField<15, 1, u32> tc_wb_action_ena;
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BitField<16, 1, u32> tcl1__action_ena;
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BitField<17, 1, u32> tc_action_ena;
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BitField<25, 2, u32> cache_policy; ///< Cache Policy setting used for writing fences and
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///< timestamps to the TCL2
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u32 dw1;
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};
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union {
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BitField<16, 2, u32> dst_sel; ///< destination select
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BitField<24, 3, InterruptSelect> int_sel; ///< selects interrupt action for end-of-pipe
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BitField<29, 3, DataSelect> data_sel; ///< selects source of data
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u32 dw2;
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};
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u32 address_lo; ///< low bits of address
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u32 address_hi; ///< high bits of address
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union {
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struct {
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u16 gds_index; ///< Byte offset into GDS to copy from
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u16 num_dw; ///< Number of DWORDS of GDS to copy
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};
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u32 data_lo; ///< value that will be written to memory when event occurs
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};
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u32 data_hi;
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template <typename T>
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T* Address() const {
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return reinterpret_cast<T*>(address_lo | u64(address_hi) << 32);
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}
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u32 DataDWord() const {
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return data_lo;
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}
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u64 DataQWord() const {
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return data_lo | u64(data_hi) << 32;
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}
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void SignalFence(Platform::InterruptId irq_id) const {
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switch (data_sel.Value()) {
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case DataSelect::Data32Low: {
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*Address<u32>() = DataDWord();
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break;
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}
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case DataSelect::Data64: {
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*Address<u64>() = DataQWord();
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break;
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}
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case DataSelect::PerfCounter: {
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*Address<u64>() = Common::FencedRDTSC();
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break;
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}
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default: {
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UNREACHABLE();
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}
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}
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switch (int_sel.Value()) {
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case InterruptSelect::None: {
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// No interrupt
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break;
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}
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case InterruptSelect::IrqUndocumented:
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[[fallthrough]];
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case InterruptSelect::IrqWhenWriteConfirm: {
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Platform::IrqC::Instance()->Signal(irq_id);
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break;
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}
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default: {
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UNREACHABLE();
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}
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}
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}
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};
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} // namespace AmdGpu
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@ -46,6 +46,7 @@ enum class PM4ItOpcode : u32 {
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EventWrite = 0x46,
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EventWriteEop = 0x47,
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EventWriteEos = 0x48,
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ReleaseMem = 0x49,
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PremableCntl = 0x4A,
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DmaData = 0x50,
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ContextRegRmw = 0x51,
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@ -108,36 +108,39 @@ constexpr std::string_view NameOf(TilingMode type) {
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}
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struct Image {
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union {
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BitField<0, 38, u64> base_address;
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BitField<40, 12, u64> min_lod;
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BitField<52, 6, u64> data_format;
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BitField<58, 4, u64> num_format;
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BitField<62, 2, u64> mtype;
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};
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union {
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BitField<0, 14, u64> width;
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BitField<14, 14, u64> height;
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BitField<28, 3, u64> perf_modulation;
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BitField<31, 1, u64> interlaced;
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BitField<32, 3, u64> dst_sel_x;
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BitField<35, 3, u64> dst_sel_y;
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BitField<38, 3, u64> dst_sel_z;
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BitField<41, 3, u64> dst_sel_w;
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BitField<44, 4, u64> base_level;
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BitField<48, 4, u64> last_level;
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BitField<52, 5, u64> tiling_index;
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BitField<57, 1, u64> pow2pad;
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BitField<58, 1, u64> mtype2;
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BitField<59, 1, u64> atc;
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BitField<60, 4, ImageType> type;
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};
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union {
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BitField<0, 13, u64> depth;
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BitField<13, 14, u64> pitch;
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BitField<32, 13, u64> base_array;
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BitField<45, 13, u64> last_array;
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};
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u64 base_address : 38;
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u64 mtype_l2 : 2;
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u64 min_lod : 12;
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u64 data_format : 6;
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u64 num_format : 4;
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u64 mtype : 2;
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u64 width : 14;
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u64 height : 14;
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u64 perf_modulation : 3;
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u64 interlaced : 1;
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u64 dst_sel_x : 3;
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u64 dst_sel_y : 3;
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u64 dst_sel_z : 3;
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u64 dst_sel_w : 3;
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u64 base_level : 4;
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u64 last_level : 4;
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u64 tiling_index : 5;
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u64 pow2pad : 1;
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u64 mtype2 : 1;
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u64 atc : 1;
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u64 type : 4;
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u64 depth : 13;
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u64 pitch : 14;
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u64 : 5;
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u64 base_array : 13;
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u64 last_array : 13;
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u64 : 6;
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u64 min_lod_warn : 12;
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u64 counter_bank_id : 8;
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u64 lod_hw_cnt_en : 1;
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u64 : 43;
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VAddr Address() const {
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return base_address << 8;
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@ -148,8 +151,8 @@ struct Image {
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}
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u32 NumLayers() const {
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u32 slices = type == ImageType::Color3D ? 1 : depth.Value() + 1;
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if (type == ImageType::Cube) {
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u32 slices = GetType() == ImageType::Color3D ? 1 : depth + 1;
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if (GetType() == ImageType::Cube) {
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slices *= 6;
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}
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if (pow2pad) {
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@ -159,33 +162,38 @@ struct Image {
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}
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u32 NumLevels() const {
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if (type == ImageType::Color2DMsaa || type == ImageType::Color2DMsaaArray) {
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if (GetType() == ImageType::Color2DMsaa || GetType() == ImageType::Color2DMsaaArray) {
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return 1;
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}
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return last_level + 1;
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}
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ImageType GetType() const noexcept {
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return static_cast<ImageType>(type);
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}
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DataFormat GetDataFmt() const noexcept {
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return static_cast<DataFormat>(data_format.Value());
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return static_cast<DataFormat>(data_format);
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}
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NumberFormat GetNumberFmt() const noexcept {
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return static_cast<NumberFormat>(num_format.Value());
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return static_cast<NumberFormat>(num_format);
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}
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[[nodiscard]] TilingMode GetTilingMode() const {
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return static_cast<TilingMode>(tiling_index.Value());
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TilingMode GetTilingMode() const {
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return static_cast<TilingMode>(tiling_index);
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}
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[[nodiscard]] bool IsTiled() const {
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bool IsTiled() const {
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return GetTilingMode() != TilingMode::Display_Linear;
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}
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[[nodiscard]] size_t GetSizeAligned() const {
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size_t GetSizeAligned() const {
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// TODO: Derive this properly from tiling params
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return (width + 1) * (height + 1) * NumComponents(GetDataFmt());
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return Pitch() * (height + 1) * NumComponents(GetDataFmt());
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}
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};
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static_assert(sizeof(Image) == 32); // 256bits
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// 8.2.7. Image Sampler [RDNA 2 Instruction Set Architecture]
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enum class ClampMode : u64 {
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@ -53,7 +53,9 @@ GraphicsPipeline::GraphicsPipeline(const Instance& instance_, Scheduler& schedul
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bindings.push_back({
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.binding = input.binding,
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.stride = buffer.GetStride(),
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.inputRate = vk::VertexInputRate::eVertex,
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.inputRate = input.instance_step_rate == Shader::Info::VsInput::None
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? vk::VertexInputRate::eVertex
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: vk::VertexInputRate::eInstance,
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});
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}
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@ -402,8 +404,11 @@ void GraphicsPipeline::BindVertexBuffers(StreamBuffer& staging) const {
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// Calculate buffers memory overlaps
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boost::container::static_vector<BufferRange, MaxVertexBufferCount> ranges{};
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for (const auto& input : vs_info.vs_inputs) {
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const auto& buffer = guest_buffers.emplace_back(
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vs_info.ReadUd<AmdGpu::Buffer>(input.sgpr_base, input.dword_offset));
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const auto& buffer = vs_info.ReadUd<AmdGpu::Buffer>(input.sgpr_base, input.dword_offset);
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if (buffer.GetSize() == 0) {
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continue;
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}
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guest_buffers.emplace_back(buffer);
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ranges.emplace_back(buffer.base_address.Value(),
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buffer.base_address.Value() + buffer.GetSize());
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}
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@ -116,11 +116,13 @@ static vk::ImageType ConvertImageType(AmdGpu::ImageType type) noexcept {
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ImageInfo::ImageInfo(const Libraries::VideoOut::BufferAttributeGroup& group) noexcept {
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const auto& attrib = group.attrib;
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is_tiled = attrib.tiling_mode == TilingMode::Tile;
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tiling_mode =
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is_tiled ? AmdGpu::TilingMode::Display_MacroTiled : AmdGpu::TilingMode::Display_Linear;
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pixel_format = ConvertPixelFormat(attrib.pixel_format);
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type = vk::ImageType::e2D;
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size.width = attrib.width;
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size.height = attrib.height;
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pitch = attrib.tiling_mode == TilingMode::Linear ? size.width : (size.width + 127) >> 7;
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pitch = attrib.tiling_mode == TilingMode::Linear ? size.width : (size.width + 127) & (~127);
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const bool is_32bpp = attrib.pixel_format != VideoOutFormat::A16R16G16B16Float;
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ASSERT(is_32bpp);
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if (!is_tiled) {
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@ -128,11 +130,11 @@ ImageInfo::ImageInfo(const Libraries::VideoOut::BufferAttributeGroup& group) noe
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return;
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}
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if (Config::isNeoMode()) {
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guest_size_bytes = pitch * 128 * ((size.height + 127) & (~127)) * 4;
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guest_size_bytes = pitch * ((size.height + 127) & (~127)) * 4;
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} else {
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guest_size_bytes = pitch * 128 * ((size.height + 63) & (~63)) * 4;
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guest_size_bytes = pitch * ((size.height + 63) & (~63)) * 4;
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}
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is_vo_surface = true;
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usage.vo_buffer = true;
|
||||
}
|
||||
|
||||
ImageInfo::ImageInfo(const AmdGpu::Liverpool::ColorBuffer& buffer,
|
||||
|
|
@ -140,12 +142,14 @@ ImageInfo::ImageInfo(const AmdGpu::Liverpool::ColorBuffer& buffer,
|
|||
is_tiled = buffer.IsTiled();
|
||||
tiling_mode = buffer.GetTilingMode();
|
||||
pixel_format = LiverpoolToVK::SurfaceFormat(buffer.info.format, buffer.NumFormat());
|
||||
num_samples = 1 << buffer.attrib.num_fragments_log2;
|
||||
type = vk::ImageType::e2D;
|
||||
size.width = hint.Valid() ? hint.width : buffer.Pitch();
|
||||
size.height = hint.Valid() ? hint.height : buffer.Height();
|
||||
size.depth = 1;
|
||||
pitch = size.width;
|
||||
guest_size_bytes = buffer.GetSizeAligned();
|
||||
usage.render_target = true;
|
||||
}
|
||||
|
||||
ImageInfo::ImageInfo(const AmdGpu::Liverpool::DepthBuffer& buffer,
|
||||
|
|
@ -153,18 +157,20 @@ ImageInfo::ImageInfo(const AmdGpu::Liverpool::DepthBuffer& buffer,
|
|||
is_tiled = false;
|
||||
pixel_format = LiverpoolToVK::DepthFormat(buffer.z_info.format, buffer.stencil_info.format);
|
||||
type = vk::ImageType::e2D;
|
||||
num_samples = 1 << buffer.z_info.num_samples; // spec doesn't say it is a log2
|
||||
size.width = hint.Valid() ? hint.width : buffer.Pitch();
|
||||
size.height = hint.Valid() ? hint.height : buffer.Height();
|
||||
size.depth = 1;
|
||||
pitch = size.width;
|
||||
guest_size_bytes = buffer.GetSizeAligned();
|
||||
usage.depth_target = true;
|
||||
}
|
||||
|
||||
ImageInfo::ImageInfo(const AmdGpu::Image& image) noexcept {
|
||||
is_tiled = image.IsTiled();
|
||||
tiling_mode = image.GetTilingMode();
|
||||
pixel_format = LiverpoolToVK::SurfaceFormat(image.GetDataFmt(), image.GetNumberFmt());
|
||||
type = ConvertImageType(image.type);
|
||||
type = ConvertImageType(image.GetType());
|
||||
size.width = image.width + 1;
|
||||
size.height = image.height + 1;
|
||||
size.depth = 1;
|
||||
|
|
@ -222,7 +228,7 @@ Image::Image(const Vulkan::Instance& instance_, Vulkan::Scheduler& scheduler_,
|
|||
}
|
||||
}
|
||||
|
||||
info.usage = ImageUsageFlags(info);
|
||||
usage = ImageUsageFlags(info);
|
||||
|
||||
if (info.pixel_format == vk::Format::eD32Sfloat) {
|
||||
aspect_mask = vk::ImageAspectFlagBits::eDepth;
|
||||
|
|
@ -243,7 +249,7 @@ Image::Image(const Vulkan::Instance& instance_, Vulkan::Scheduler& scheduler_,
|
|||
.mipLevels = static_cast<u32>(info.resources.levels),
|
||||
.arrayLayers = static_cast<u32>(info.resources.layers),
|
||||
.tiling = vk::ImageTiling::eOptimal,
|
||||
.usage = info.usage,
|
||||
.usage = usage,
|
||||
.initialLayout = vk::ImageLayout::eUndefined,
|
||||
};
|
||||
|
||||
|
|
@ -296,6 +302,31 @@ void Image::Transit(vk::ImageLayout dst_layout, vk::Flags<vk::AccessFlagBits> ds
|
|||
pl_stage = dst_pl_stage;
|
||||
}
|
||||
|
||||
void Image::Upload(vk::Buffer buffer, u64 offset) {
|
||||
Transit(vk::ImageLayout::eTransferDstOptimal, vk::AccessFlagBits::eTransferWrite);
|
||||
|
||||
// Copy to the image.
|
||||
const vk::BufferImageCopy image_copy = {
|
||||
.bufferOffset = offset,
|
||||
.bufferRowLength = info.pitch,
|
||||
.bufferImageHeight = info.size.height,
|
||||
.imageSubresource{
|
||||
.aspectMask = vk::ImageAspectFlagBits::eColor,
|
||||
.mipLevel = 0,
|
||||
.baseArrayLayer = 0,
|
||||
.layerCount = 1,
|
||||
},
|
||||
.imageOffset = {0, 0, 0},
|
||||
.imageExtent = {info.size.width, info.size.height, 1},
|
||||
};
|
||||
|
||||
const auto cmdbuf = scheduler->CommandBuffer();
|
||||
cmdbuf.copyBufferToImage(buffer, image, vk::ImageLayout::eTransferDstOptimal, image_copy);
|
||||
|
||||
Transit(vk::ImageLayout::eGeneral,
|
||||
vk::AccessFlagBits::eShaderRead | vk::AccessFlagBits::eTransferRead);
|
||||
}
|
||||
|
||||
Image::~Image() = default;
|
||||
|
||||
} // namespace VideoCore
|
||||
|
|
|
|||
|
|
@ -42,18 +42,28 @@ struct ImageInfo {
|
|||
const AmdGpu::Liverpool::CbDbExtent& hint = {}) noexcept;
|
||||
explicit ImageInfo(const AmdGpu::Image& image) noexcept;
|
||||
|
||||
bool IsTiled() const {
|
||||
return tiling_mode != AmdGpu::TilingMode::Display_Linear;
|
||||
}
|
||||
bool IsBlockCoded() const;
|
||||
bool IsPacked() const;
|
||||
bool IsDepthStencil() const;
|
||||
|
||||
struct {
|
||||
u32 texture : 1;
|
||||
u32 storage : 1;
|
||||
u32 render_target : 1;
|
||||
u32 depth_target : 1;
|
||||
u32 vo_buffer : 1;
|
||||
} usage; // Usage data tracked during image lifetime
|
||||
|
||||
bool is_tiled = false;
|
||||
bool is_storage = false;
|
||||
bool is_vo_surface = false;
|
||||
vk::Format pixel_format = vk::Format::eUndefined;
|
||||
vk::ImageType type = vk::ImageType::e1D;
|
||||
vk::ImageUsageFlags usage;
|
||||
SubresourceExtent resources;
|
||||
Extent3D size{1, 1, 1};
|
||||
u32 num_samples = 1;
|
||||
u32 pitch = 0;
|
||||
u32 guest_size_bytes = 0;
|
||||
AmdGpu::TilingMode tiling_mode{AmdGpu::TilingMode::Display_Linear};
|
||||
|
|
@ -117,6 +127,7 @@ struct Image {
|
|||
}
|
||||
|
||||
void Transit(vk::ImageLayout dst_layout, vk::Flags<vk::AccessFlagBits> dst_mask);
|
||||
void Upload(vk::Buffer buffer, u64 offset);
|
||||
|
||||
const Vulkan::Instance* instance;
|
||||
Vulkan::Scheduler* scheduler;
|
||||
|
|
@ -131,6 +142,7 @@ struct Image {
|
|||
std::optional<ImageView> view_for_detiler;
|
||||
|
||||
// Resource state tracking
|
||||
vk::ImageUsageFlags usage;
|
||||
vk::Flags<vk::PipelineStageFlagBits> pl_stage = vk::PipelineStageFlagBits::eAllCommands;
|
||||
vk::Flags<vk::AccessFlagBits> access_mask = vk::AccessFlagBits::eNone;
|
||||
vk::ImageLayout layout = vk::ImageLayout::eUndefined;
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ vk::ComponentSwizzle ConvertComponentSwizzle(u32 dst_sel) {
|
|||
|
||||
ImageViewInfo::ImageViewInfo(const AmdGpu::Image& image, bool is_storage) noexcept
|
||||
: is_storage{is_storage} {
|
||||
type = ConvertImageViewType(image.type);
|
||||
type = ConvertImageViewType(image.GetType());
|
||||
format = Vulkan::LiverpoolToVK::SurfaceFormat(image.GetDataFmt(), image.GetNumberFmt());
|
||||
range.base.level = 0;
|
||||
range.base.layer = 0;
|
||||
|
|
|
|||
|
|
@ -151,7 +151,7 @@ ImageView& TextureCache::RegisterImageView(Image& image, const ImageViewInfo& vi
|
|||
// temporary remove its storage bit.
|
||||
std::optional<vk::ImageUsageFlags> usage_override;
|
||||
if (!image.info.is_storage) {
|
||||
usage_override = image.info.usage & ~vk::ImageUsageFlagBits::eStorage;
|
||||
usage_override = image.usage & ~vk::ImageUsageFlagBits::eStorage;
|
||||
}
|
||||
|
||||
const ImageViewId view_id = slot_image_views.insert(instance, view_info, image, usage_override);
|
||||
|
|
@ -183,7 +183,7 @@ ImageView& TextureCache::RenderTarget(const AmdGpu::Liverpool::ColorBuffer& buff
|
|||
vk::AccessFlagBits::eColorAttachmentWrite |
|
||||
vk::AccessFlagBits::eColorAttachmentRead);
|
||||
|
||||
ImageViewInfo view_info{buffer, image.info.is_vo_surface};
|
||||
ImageViewInfo view_info{buffer, !!image.info.usage.vo_buffer};
|
||||
return RegisterImageView(image, view_info);
|
||||
}
|
||||
|
||||
|
|
@ -210,26 +210,8 @@ void TextureCache::RefreshImage(Image& image) {
|
|||
if (!tile_manager.TryDetile(image)) {
|
||||
// Upload data to the staging buffer.
|
||||
const auto offset = staging.Copy(image.cpu_addr, image.info.guest_size_bytes, 4);
|
||||
image.Transit(vk::ImageLayout::eTransferDstOptimal, vk::AccessFlagBits::eTransferWrite);
|
||||
|
||||
// Copy to the image.
|
||||
const vk::BufferImageCopy image_copy = {
|
||||
.bufferOffset = offset,
|
||||
.bufferRowLength = 0,
|
||||
.bufferImageHeight = 0,
|
||||
.imageSubresource{
|
||||
.aspectMask = vk::ImageAspectFlagBits::eColor,
|
||||
.mipLevel = 0,
|
||||
.baseArrayLayer = 0,
|
||||
.layerCount = 1,
|
||||
},
|
||||
.imageOffset = {0, 0, 0},
|
||||
.imageExtent = {image.info.size.width, image.info.size.height, 1},
|
||||
};
|
||||
|
||||
const auto cmdbuf = scheduler.CommandBuffer();
|
||||
cmdbuf.copyBufferToImage(staging.Handle(), image.image,
|
||||
vk::ImageLayout::eTransferDstOptimal, image_copy);
|
||||
image.Upload(staging.Handle(), offset);
|
||||
}
|
||||
|
||||
image.Transit(vk::ImageLayout::eGeneral,
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@
|
|||
|
||||
#include <boost/container/static_vector.hpp>
|
||||
#include <magic_enum.hpp>
|
||||
#include <vulkan/vulkan_to_string.hpp>
|
||||
|
||||
namespace VideoCore {
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue