Stub PM4 COPY_DATA opcode (#3032)

src/video_core/amdgpu/liverpool.cpp

@@ -394,7 +394,7 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
                 break;
             }
             case PM4ItOpcode::SetPredication: {
-                LOG_WARNING(Render_Vulkan, "Unimplemented IT_SET_PREDICATION");
+                LOG_WARNING(Render, "Unimplemented IT_SET_PREDICATION");
                 break;
             }
             case PM4ItOpcode::IndexType: {
@@ -586,8 +586,7 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
             }
             case PM4ItOpcode::EventWrite: {
                 const auto* event = reinterpret_cast<const PM4CmdEventWrite*>(header);
-                LOG_DEBUG(Render_Vulkan,
+                LOG_DEBUG(Render, "Encountered EventWrite: event_type = {}, event_index = {}",
-                          "Encountered EventWrite: event_type = {}, event_index = {}",
                           magic_enum::enum_name(event->event_type.Value()),
                           magic_enum::enum_name(event->event_index.Value()));
                 if (event->event_type.Value() == EventType::SoVgtStreamoutFlush) {
@@ -673,6 +672,16 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
                 }
                 break;
             }
+            case PM4ItOpcode::CopyData: {
+                const auto* copy_data = reinterpret_cast<const PM4CmdCopyData*>(header);
+                LOG_WARNING(Render,
+                            "unhandled IT_COPY_DATA src_sel = {}, dst_sel = {}, "
+                            "count_sel = {}, wr_confirm = {}, engine_sel = {}",
+                            u32(copy_data->src_sel.Value()), u32(copy_data->dst_sel.Value()),
+                            copy_data->count_sel.Value(), copy_data->wr_confirm.Value(),
+                            u32(copy_data->engine_sel.Value()));
+                break;
+            }
             case PM4ItOpcode::MemSemaphore: {
                 const auto* mem_semaphore = reinterpret_cast<const PM4CmdMemSemaphore*>(header);
                 if (mem_semaphore->IsSignaling()) {

src/video_core/amdgpu/pm4_cmds.h

@@ -554,6 +554,61 @@ struct PM4DmaData {
     }
 };
 
+enum class CopyDataSrc : u32 {
+    MappedRegister = 0,
+    Memory = 1,
+    TCL2 = 2,
+    Gds = 3,
+    // Reserved = 4,
+    Immediate = 5,
+    Atomic = 6,
+    GdsAtomic0 = 7,
+    GdsAtomic1 = 8,
+    GpuClock = 9,
+};
+
+enum class CopyDataDst : u32 {
+    MappedRegister = 0,
+    MemorySync = 1,
+    TCL2 = 2,
+    Gds = 3,
+    // Reserved = 4,
+    MemoryAsync = 5,
+};
+
+enum class CopyDataEngine : u32 {
+    Me = 0,
+    Pfp = 1,
+    Ce = 2,
+    // Reserved = 3
+};
+
+struct PM4CmdCopyData {
+    PM4Type3Header header;
+    union {
+        BitField<0, 4, CopyDataSrc> src_sel;
+        BitField<8, 4, CopyDataDst> dst_sel;
+        BitField<16, 1, u32> count_sel;
+        BitField<20, 1, u32> wr_confirm;
+        BitField<30, 2, CopyDataEngine> engine_sel;
+        u32 control;
+    };
+    u32 src_addr_lo;
+    u32 src_addr_hi;
+    u32 dst_addr_lo;
+    u32 dst_addr_hi;
+
+    template <typename T>
+    T SrcAddress() const {
+        return std::bit_cast<T>(src_addr_lo | u64(src_addr_hi) << 32);
+    }
+
+    template <typename T>
+    T DstAddress() const {
+        return std::bit_cast<T>(dst_addr_lo | u64(dst_addr_hi) << 32);
+    }
+};
+
 struct PM4CmdRewind {
     PM4Type3Header header;
     union {