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shader_recompiler: Move sampling parameter resolution to tracking pass and support more derivative types. (#1290)
* shader_recompiler: Move sampling parameter resolution to tracking pass and support more derivative types. * shader_recompiler: Only track sampler sharp on sample instructions. * shader_recompiler: Fix Inst args size.
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squidbus
GitHub
parent
fd4893f6ef
commit
d91ad6174e
10 changed files with 338 additions and 272 deletions
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@ -411,7 +411,7 @@ void Translator::IMAGE_LOAD(bool has_mip, const GcnInst& inst) {
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ir.GetVectorReg(addr_reg + 2), ir.GetVectorReg(addr_reg + 3));
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IR::TextureInstInfo info{};
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info.explicit_lod.Assign(has_mip);
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info.has_lod.Assign(has_mip);
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const IR::Value texel = ir.ImageFetch(handle, body, {}, {}, {}, info);
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for (u32 i = 0; i < 4; i++) {
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@ -513,6 +513,76 @@ void Translator::IMAGE_ATOMIC(AtomicOp op, const GcnInst& inst) {
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}
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}
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IR::Value EmitImageSample(IR::IREmitter& ir, const GcnInst& inst, const IR::ScalarReg tsharp_reg,
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const IR::ScalarReg sampler_reg, const IR::VectorReg addr_reg,
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bool gather) {
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const auto& mimg = inst.control.mimg;
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const auto flags = MimgModifierFlags(mimg.mod);
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IR::TextureInstInfo info{};
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info.is_depth.Assign(flags.test(MimgModifier::Pcf));
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info.has_bias.Assign(flags.test(MimgModifier::LodBias));
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info.has_lod_clamp.Assign(flags.test(MimgModifier::LodClamp));
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info.force_level0.Assign(flags.test(MimgModifier::Level0));
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info.has_offset.Assign(flags.test(MimgModifier::Offset));
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info.has_lod.Assign(flags.any(MimgModifier::Lod));
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info.is_array.Assign(mimg.da);
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if (gather) {
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info.gather_comp.Assign(std::bit_width(mimg.dmask) - 1);
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info.is_gather.Assign(true);
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} else {
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info.has_derivatives.Assign(flags.test(MimgModifier::Derivative));
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}
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// Load first dword of T# and S#. We will use them as the handle that will guide resource
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// tracking pass where to read the sharps. This will later also get patched to the SPIRV texture
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// binding index.
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const IR::Value handle =
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ir.CompositeConstruct(ir.GetScalarReg(tsharp_reg), ir.GetScalarReg(sampler_reg));
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// Determine how many address registers need to be passed.
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// The image type is unknown, so add all 4 possible base registers and resolve later.
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int num_addr_regs = 4;
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if (info.has_offset) {
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++num_addr_regs;
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}
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if (info.has_bias) {
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++num_addr_regs;
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}
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if (info.is_depth) {
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++num_addr_regs;
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}
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if (info.has_derivatives) {
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// The image type is unknown, so add all 6 possible derivative registers and resolve later.
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num_addr_regs += 6;
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}
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// Fetch all the address registers to pass in the IR instruction. There can be up to 13
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// registers.
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const auto get_addr_reg = [&](int index) -> IR::F32 {
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if (index >= num_addr_regs) {
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return ir.Imm32(0.f);
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}
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return ir.GetVectorReg<IR::F32>(addr_reg + index);
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};
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const IR::Value address1 =
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ir.CompositeConstruct(get_addr_reg(0), get_addr_reg(1), get_addr_reg(2), get_addr_reg(3));
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const IR::Value address2 =
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ir.CompositeConstruct(get_addr_reg(4), get_addr_reg(5), get_addr_reg(6), get_addr_reg(7));
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const IR::Value address3 =
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ir.CompositeConstruct(get_addr_reg(8), get_addr_reg(9), get_addr_reg(10), get_addr_reg(11));
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const IR::Value address4 = get_addr_reg(12);
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// Issue the placeholder IR instruction.
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IR::Value texel = ir.ImageSampleRaw(handle, address1, address2, address3, address4, info);
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if (info.is_depth && !gather) {
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// For non-gather depth sampling, only return a single value.
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texel = ir.CompositeExtract(texel, 0);
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}
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return texel;
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}
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void Translator::IMAGE_SAMPLE(const GcnInst& inst) {
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const auto& mimg = inst.control.mimg;
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IR::VectorReg addr_reg{inst.src[0].code};
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@ -521,72 +591,7 @@ void Translator::IMAGE_SAMPLE(const GcnInst& inst) {
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const IR::ScalarReg sampler_reg{inst.src[3].code * 4};
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const auto flags = MimgModifierFlags(mimg.mod);
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// Load first dword of T# and S#. We will use them as the handle that will guide resource
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// tracking pass where to read the sharps. This will later also get patched to the SPIRV texture
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// binding index.
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const IR::Value handle =
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ir.CompositeConstruct(ir.GetScalarReg(tsharp_reg), ir.GetScalarReg(sampler_reg));
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// Load first address components as denoted in 8.2.4 VGPR Usage Sea Islands Series Instruction
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// Set Architecture
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const IR::U32 offset =
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flags.test(MimgModifier::Offset) ? ir.GetVectorReg<IR::U32>(addr_reg++) : IR::U32{};
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const IR::F32 bias =
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flags.test(MimgModifier::LodBias) ? ir.GetVectorReg<IR::F32>(addr_reg++) : IR::F32{};
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const IR::F32 dref =
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flags.test(MimgModifier::Pcf) ? ir.GetVectorReg<IR::F32>(addr_reg++) : IR::F32{};
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const IR::Value derivatives = [&] -> IR::Value {
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if (!flags.test(MimgModifier::Derivative)) {
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return {};
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}
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addr_reg = addr_reg + 4;
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return ir.CompositeConstruct(
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ir.GetVectorReg<IR::F32>(addr_reg - 4), ir.GetVectorReg<IR::F32>(addr_reg - 3),
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ir.GetVectorReg<IR::F32>(addr_reg - 2), ir.GetVectorReg<IR::F32>(addr_reg - 1));
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}();
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// Now we can load body components as noted in Table 8.9 Image Opcodes with Sampler
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// Since these are at most 4 dwords, we load them into a single uvec4 and place them
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// in coords field of the instruction. Then the resource tracking pass will patch the
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// IR instruction to fill in lod_clamp field.
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const IR::Value body = ir.CompositeConstruct(
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ir.GetVectorReg<IR::F32>(addr_reg), ir.GetVectorReg<IR::F32>(addr_reg + 1),
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ir.GetVectorReg<IR::F32>(addr_reg + 2), ir.GetVectorReg<IR::F32>(addr_reg + 3));
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// Derivatives are tricky because their number depends on the texture type which is located in
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// T#. We don't have access to T# though until resource tracking pass. For now assume if
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// derivatives are present, that a 2D image is bound.
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const bool has_derivatives = flags.test(MimgModifier::Derivative);
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const bool explicit_lod = flags.any(MimgModifier::Level0, MimgModifier::Lod);
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IR::TextureInstInfo info{};
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info.is_depth.Assign(flags.test(MimgModifier::Pcf));
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info.has_bias.Assign(flags.test(MimgModifier::LodBias));
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info.has_lod_clamp.Assign(flags.test(MimgModifier::LodClamp));
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info.force_level0.Assign(flags.test(MimgModifier::Level0));
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info.has_offset.Assign(flags.test(MimgModifier::Offset));
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info.explicit_lod.Assign(explicit_lod);
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info.has_derivatives.Assign(has_derivatives);
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info.is_array.Assign(mimg.da);
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// Issue IR instruction, leaving unknown fields blank to patch later.
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const IR::Value texel = [&]() -> IR::Value {
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if (has_derivatives) {
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return ir.ImageGradient(handle, body, derivatives, offset, {}, info);
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}
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if (!flags.test(MimgModifier::Pcf)) {
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if (explicit_lod) {
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return ir.ImageSampleExplicitLod(handle, body, offset, info);
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} else {
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return ir.ImageSampleImplicitLod(handle, body, bias, offset, info);
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}
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}
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if (explicit_lod) {
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return ir.ImageSampleDrefExplicitLod(handle, body, dref, offset, info);
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}
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return ir.ImageSampleDrefImplicitLod(handle, body, dref, bias, offset, info);
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}();
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const IR::Value texel = EmitImageSample(ir, inst, tsharp_reg, sampler_reg, addr_reg, false);
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for (u32 i = 0; i < 4; i++) {
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if (((mimg.dmask >> i) & 1) == 0) {
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continue;
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@ -609,60 +614,13 @@ void Translator::IMAGE_GATHER(const GcnInst& inst) {
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const IR::ScalarReg sampler_reg{inst.src[3].code * 4};
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const auto flags = MimgModifierFlags(mimg.mod);
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// Load first dword of T# and S#. We will use them as the handle that will guide resource
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// tracking pass where to read the sharps. This will later also get patched to the SPIRV texture
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// binding index.
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const IR::Value handle =
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ir.CompositeConstruct(ir.GetScalarReg(tsharp_reg), ir.GetScalarReg(sampler_reg));
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// Load first address components as denoted in 8.2.4 VGPR Usage Sea Islands Series Instruction
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// Set Architecture
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const IR::Value offset =
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flags.test(MimgModifier::Offset) ? ir.GetVectorReg(addr_reg++) : IR::Value{};
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const IR::F32 bias =
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flags.test(MimgModifier::LodBias) ? ir.GetVectorReg<IR::F32>(addr_reg++) : IR::F32{};
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const IR::F32 dref =
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flags.test(MimgModifier::Pcf) ? ir.GetVectorReg<IR::F32>(addr_reg++) : IR::F32{};
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// Derivatives are tricky because their number depends on the texture type which is located in
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// T#. We don't have access to T# though until resource tracking pass. For now assume no
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// derivatives are present, otherwise we don't know where coordinates are placed in the address
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// stream.
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ASSERT_MSG(!flags.test(MimgModifier::Derivative), "Derivative image instruction");
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// Now we can load body components as noted in Table 8.9 Image Opcodes with Sampler
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// Since these are at most 4 dwords, we load them into a single uvec4 and place them
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// in coords field of the instruction. Then the resource tracking pass will patch the
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// IR instruction to fill in lod_clamp field.
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const IR::Value body = ir.CompositeConstruct(
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ir.GetVectorReg<IR::F32>(addr_reg), ir.GetVectorReg<IR::F32>(addr_reg + 1),
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ir.GetVectorReg<IR::F32>(addr_reg + 2), ir.GetVectorReg<IR::F32>(addr_reg + 3));
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const bool explicit_lod = flags.any(MimgModifier::Level0, MimgModifier::Lod);
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IR::TextureInstInfo info{};
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info.is_depth.Assign(flags.test(MimgModifier::Pcf));
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info.has_bias.Assign(flags.test(MimgModifier::LodBias));
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info.has_lod_clamp.Assign(flags.test(MimgModifier::LodClamp));
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info.force_level0.Assign(flags.test(MimgModifier::Level0));
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info.has_offset.Assign(flags.test(MimgModifier::Offset));
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// info.explicit_lod.Assign(explicit_lod);
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info.gather_comp.Assign(std::bit_width(mimg.dmask) - 1);
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info.is_array.Assign(mimg.da);
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// Issue IR instruction, leaving unknown fields blank to patch later.
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const IR::Value texel = [&]() -> IR::Value {
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const IR::F32 lod = flags.test(MimgModifier::Level0) ? ir.Imm32(0.f) : IR::F32{};
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if (!flags.test(MimgModifier::Pcf)) {
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return ir.ImageGather(handle, body, offset, info);
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}
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ASSERT(mimg.dmask & 1); // should be always 1st (R) component
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return ir.ImageGatherDref(handle, body, offset, dref, info);
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}();
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// For gather4 instructions dmask selects which component to read and must have
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// only one bit set to 1
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ASSERT_MSG(std::popcount(mimg.dmask) == 1, "Unexpected bits in gather dmask");
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// should be always 1st (R) component for depth
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ASSERT(!flags.test(MimgModifier::Pcf) || mimg.dmask & 1);
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const IR::Value texel = EmitImageSample(ir, inst, tsharp_reg, sampler_reg, addr_reg, true);
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for (u32 i = 0; i < 4; i++) {
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const IR::F32 value = IR::F32{ir.CompositeExtract(texel, i)};
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ir.SetVectorReg(dest_reg++, value);
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