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https://github.com/shadps4-emu/shadPS4.git
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shader_recompiler: Move sampling parameter resolution to tracking pass and support more derivative types. (#1290)
* shader_recompiler: Move sampling parameter resolution to tracking pass and support more derivative types. * shader_recompiler: Only track sampler sharp on sample instructions. * shader_recompiler: Fix Inst args size.
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squidbus
GitHub
parent
fd4893f6ef
commit
d91ad6174e
10 changed files with 338 additions and 272 deletions
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@ -132,38 +132,16 @@ bool IsImageStorageInstruction(const IR::Inst& inst) {
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bool IsImageInstruction(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::ImageSampleExplicitLod:
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case IR::Opcode::ImageSampleImplicitLod:
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case IR::Opcode::ImageSampleDrefExplicitLod:
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case IR::Opcode::ImageSampleDrefImplicitLod:
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case IR::Opcode::ImageFetch:
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case IR::Opcode::ImageGather:
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case IR::Opcode::ImageGatherDref:
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case IR::Opcode::ImageQueryDimensions:
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case IR::Opcode::ImageQueryLod:
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case IR::Opcode::ImageGradient:
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case IR::Opcode::ImageSampleRaw:
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return true;
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default:
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return IsImageStorageInstruction(inst);
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}
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}
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u32 ImageOffsetArgumentPosition(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::ImageGather:
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case IR::Opcode::ImageGatherDref:
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return 2;
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case IR::Opcode::ImageSampleExplicitLod:
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case IR::Opcode::ImageSampleImplicitLod:
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return 3;
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case IR::Opcode::ImageSampleDrefExplicitLod:
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case IR::Opcode::ImageSampleDrefImplicitLod:
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return 4;
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default:
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UNREACHABLE();
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}
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}
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class Descriptors {
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public:
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explicit Descriptors(Info& info_)
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@ -467,6 +445,185 @@ IR::Value PatchCubeCoord(IR::IREmitter& ir, const IR::Value& s, const IR::Value&
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}
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}
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void PatchImageSampleInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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Descriptors& descriptors, const IR::Inst* producer,
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const u32 image_binding, const AmdGpu::Image& image) {
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// Read sampler sharp. This doesn't exist for IMAGE_LOAD/IMAGE_STORE instructions
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const u32 sampler_binding = [&] {
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ASSERT(producer->GetOpcode() == IR::Opcode::CompositeConstructU32x2);
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const IR::Value& handle = producer->Arg(1);
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// Inline sampler resource.
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if (handle.IsImmediate()) {
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LOG_WARNING(Render_Vulkan, "Inline sampler detected");
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return descriptors.Add(SamplerResource{
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.sgpr_base = std::numeric_limits<u32>::max(),
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.dword_offset = 0,
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.inline_sampler = AmdGpu::Sampler{.raw0 = handle.U32()},
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});
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}
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// Normal sampler resource.
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const auto ssharp_handle = handle.InstRecursive();
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const auto& [ssharp_ud, disable_aniso] = TryDisableAnisoLod0(ssharp_handle);
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const auto ssharp = TrackSharp(ssharp_ud);
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return descriptors.Add(SamplerResource{
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.sgpr_base = ssharp.sgpr_base,
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.dword_offset = ssharp.dword_offset,
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.associated_image = image_binding,
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.disable_aniso = disable_aniso,
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});
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}();
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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const auto inst_info = inst.Flags<IR::TextureInstInfo>();
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const IR::U32 handle = ir.Imm32(image_binding | sampler_binding << 16);
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IR::Inst* body1 = inst.Arg(1).InstRecursive();
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IR::Inst* body2 = inst.Arg(2).InstRecursive();
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IR::Inst* body3 = inst.Arg(3).InstRecursive();
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IR::Inst* body4 = inst.Arg(4).InstRecursive();
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const auto get_addr_reg = [&](u32 index) -> IR::F32 {
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if (index <= 3) {
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return IR::F32{body1->Arg(index)};
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}
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if (index >= 4 && index <= 7) {
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return IR::F32{body2->Arg(index - 4)};
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}
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if (index >= 8 && index <= 11) {
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return IR::F32{body3->Arg(index - 8)};
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}
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if (index == 12) {
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return IR::F32{body4};
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}
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UNREACHABLE();
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};
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u32 addr_reg = 0;
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// Load first address components as denoted in 8.2.4 VGPR Usage Sea Islands Series Instruction
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// Set Architecture
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const IR::Value offset = [&] -> IR::Value {
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if (!inst_info.has_offset) {
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return IR::U32{};
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}
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// The offsets are six-bit signed integers: X=[5:0], Y=[13:8], and Z=[21:16].
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const IR::Value arg = get_addr_reg(addr_reg++);
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const auto read = [&](u32 off) -> IR::U32 {
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if (arg.IsImmediate()) {
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const u16 comp = (arg.U32() >> off) & 0x3F;
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return ir.Imm32(s32(comp << 26) >> 26);
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}
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return ir.BitFieldExtract(IR::U32{arg}, ir.Imm32(off), ir.Imm32(6), true);
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};
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switch (image.GetType()) {
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case AmdGpu::ImageType::Color1D:
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case AmdGpu::ImageType::Color1DArray:
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return read(0);
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case AmdGpu::ImageType::Color2D:
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case AmdGpu::ImageType::Color2DArray:
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case AmdGpu::ImageType::Color2DMsaa:
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return ir.CompositeConstruct(read(0), read(8));
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case AmdGpu::ImageType::Color3D:
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case AmdGpu::ImageType::Cube:
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return ir.CompositeConstruct(read(0), read(8), read(16));
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default:
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UNREACHABLE();
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}
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}();
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const IR::F32 bias = inst_info.has_bias ? get_addr_reg(addr_reg++) : IR::F32{};
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const IR::F32 dref = inst_info.is_depth ? get_addr_reg(addr_reg++) : IR::F32{};
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const auto [derivatives_dx, derivatives_dy] = [&] -> std::pair<IR::Value, IR::Value> {
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if (!inst_info.has_derivatives) {
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return {};
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}
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switch (image.GetType()) {
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case AmdGpu::ImageType::Color1D:
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case AmdGpu::ImageType::Color1DArray:
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// du/dx, du/dy
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addr_reg = addr_reg + 2;
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return {get_addr_reg(addr_reg - 2), get_addr_reg(addr_reg - 1)};
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case AmdGpu::ImageType::Color2D:
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case AmdGpu::ImageType::Color2DArray:
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case AmdGpu::ImageType::Color2DMsaa:
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// (du/dx, dv/dx), (du/dy, dv/dy)
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addr_reg = addr_reg + 4;
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return {ir.CompositeConstruct(get_addr_reg(addr_reg - 4), get_addr_reg(addr_reg - 3)),
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ir.CompositeConstruct(get_addr_reg(addr_reg - 2), get_addr_reg(addr_reg - 1))};
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case AmdGpu::ImageType::Color3D:
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case AmdGpu::ImageType::Cube:
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// (du/dx, dv/dx, dw/dx), (du/dy, dv/dy, dw/dy)
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addr_reg = addr_reg + 6;
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return {ir.CompositeConstruct(get_addr_reg(addr_reg - 6), get_addr_reg(addr_reg - 5),
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get_addr_reg(addr_reg - 4)),
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ir.CompositeConstruct(get_addr_reg(addr_reg - 3), get_addr_reg(addr_reg - 2),
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get_addr_reg(addr_reg - 1))};
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default:
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UNREACHABLE();
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}
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}();
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// Now we can load body components as noted in Table 8.9 Image Opcodes with Sampler
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const IR::Value coords = [&] -> IR::Value {
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switch (image.GetType()) {
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case AmdGpu::ImageType::Color1D: // x
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addr_reg = addr_reg + 1;
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return get_addr_reg(addr_reg - 1);
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case AmdGpu::ImageType::Color1DArray: // x, slice
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[[fallthrough]];
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case AmdGpu::ImageType::Color2D: // x, y
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addr_reg = addr_reg + 2;
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return ir.CompositeConstruct(get_addr_reg(addr_reg - 2), get_addr_reg(addr_reg - 1));
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case AmdGpu::ImageType::Color2DArray: // x, y, slice
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[[fallthrough]];
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case AmdGpu::ImageType::Color2DMsaa: // x, y, frag
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[[fallthrough]];
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case AmdGpu::ImageType::Color3D: // x, y, z
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addr_reg = addr_reg + 3;
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return ir.CompositeConstruct(get_addr_reg(addr_reg - 3), get_addr_reg(addr_reg - 2),
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get_addr_reg(addr_reg - 1));
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case AmdGpu::ImageType::Cube: // x, y, face
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addr_reg = addr_reg + 3;
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return PatchCubeCoord(ir, get_addr_reg(addr_reg - 3), get_addr_reg(addr_reg - 2),
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get_addr_reg(addr_reg - 1), false, inst_info.is_array);
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default:
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UNREACHABLE();
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}
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}();
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ASSERT(!inst_info.has_lod || !inst_info.has_lod_clamp);
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const bool explicit_lod = inst_info.has_lod || inst_info.force_level0;
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const IR::F32 lod = inst_info.has_lod ? get_addr_reg(addr_reg++)
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: inst_info.force_level0 ? ir.Imm32(0.0f)
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: IR::F32{};
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const IR::F32 lod_clamp = inst_info.has_lod_clamp ? get_addr_reg(addr_reg++) : IR::F32{};
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const auto new_inst = [&] -> IR::Value {
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if (inst_info.is_gather) {
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if (inst_info.is_depth) {
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return ir.ImageGatherDref(handle, coords, offset, dref, inst_info);
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}
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return ir.ImageGather(handle, coords, offset, inst_info);
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}
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if (inst_info.has_derivatives) {
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return ir.ImageGradient(handle, coords, derivatives_dx, derivatives_dy, offset,
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lod_clamp, inst_info);
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}
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if (inst_info.is_depth) {
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if (explicit_lod) {
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return ir.ImageSampleDrefExplicitLod(handle, coords, dref, lod, offset, inst_info);
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}
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return ir.ImageSampleDrefImplicitLod(handle, coords, dref, bias, offset, inst_info);
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}
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if (explicit_lod) {
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return ir.ImageSampleExplicitLod(handle, coords, lod, offset, inst_info);
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}
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return ir.ImageSampleImplicitLod(handle, coords, bias, offset, inst_info);
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}();
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inst.ReplaceUsesWith(new_inst);
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}
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void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descriptors& descriptors) {
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const auto pred = [](const IR::Inst* inst) -> std::optional<const IR::Inst*> {
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const auto opcode = inst->GetOpcode();
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@ -498,40 +655,18 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
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.sgpr_base = tsharp.sgpr_base,
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.dword_offset = tsharp.dword_offset,
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.type = type,
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.nfmt = static_cast<AmdGpu::NumberFormat>(image.GetNumberFmt()),
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.nfmt = image.GetNumberFmt(),
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.is_storage = is_storage,
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.is_depth = bool(inst_info.is_depth),
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.is_atomic = IsImageAtomicInstruction(inst),
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.is_array = bool(inst_info.is_array),
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});
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// Read sampler sharp. This doesn't exist for IMAGE_LOAD/IMAGE_STORE instructions
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const u32 sampler_binding = [&] {
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if (!has_sampler) {
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return 0U;
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}
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const IR::Value& handle = producer->Arg(1);
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// Inline sampler resource.
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if (handle.IsImmediate()) {
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LOG_WARNING(Render_Vulkan, "Inline sampler detected");
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return descriptors.Add(SamplerResource{
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.sgpr_base = std::numeric_limits<u32>::max(),
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.dword_offset = 0,
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.inline_sampler = AmdGpu::Sampler{.raw0 = handle.U32()},
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});
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}
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// Normal sampler resource.
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const auto ssharp_handle = handle.InstRecursive();
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const auto& [ssharp_ud, disable_aniso] = TryDisableAnisoLod0(ssharp_handle);
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const auto ssharp = TrackSharp(ssharp_ud);
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return descriptors.Add(SamplerResource{
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.sgpr_base = ssharp.sgpr_base,
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.dword_offset = ssharp.dword_offset,
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.associated_image = image_binding,
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.disable_aniso = disable_aniso,
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});
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}();
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image_binding |= (sampler_binding << 16);
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// Sample instructions must be resolved into a new instruction using address register data.
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if (inst.GetOpcode() == IR::Opcode::ImageSampleRaw) {
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PatchImageSampleInstruction(block, inst, info, descriptors, producer, image_binding, image);
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return;
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}
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// Patch image handle
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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@ -568,62 +703,9 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
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}();
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inst.SetArg(1, coords);
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if (inst_info.has_offset) {
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// The offsets are six-bit signed integers: X=[5:0], Y=[13:8], and Z=[21:16].
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const u32 arg_pos = ImageOffsetArgumentPosition(inst);
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const IR::Value arg = inst.Arg(arg_pos);
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ASSERT_MSG(arg.Type() == IR::Type::U32, "Unexpected offset type");
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const auto read = [&](u32 offset) -> IR::U32 {
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if (arg.IsImmediate()) {
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const u16 comp = (arg.U32() >> offset) & 0x3F;
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return ir.Imm32(s32(comp << 26) >> 26);
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}
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return ir.BitFieldExtract(IR::U32{arg}, ir.Imm32(offset), ir.Imm32(6), true);
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};
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switch (image.GetType()) {
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case AmdGpu::ImageType::Color1D:
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case AmdGpu::ImageType::Color1DArray:
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inst.SetArg(arg_pos, read(0));
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break;
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case AmdGpu::ImageType::Color2D:
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case AmdGpu::ImageType::Color2DArray:
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inst.SetArg(arg_pos, ir.CompositeConstruct(read(0), read(8)));
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break;
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case AmdGpu::ImageType::Color3D:
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inst.SetArg(arg_pos, ir.CompositeConstruct(read(0), read(8), read(16)));
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break;
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default:
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UNREACHABLE();
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}
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}
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if (inst_info.has_derivatives) {
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ASSERT_MSG(image.GetType() == AmdGpu::ImageType::Color2D ||
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image.GetType() == AmdGpu::ImageType::Color2DArray,
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"User derivatives only supported for 2D images");
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}
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if (inst_info.has_lod_clamp) {
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const u32 arg_pos = [&]() -> u32 {
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switch (inst.GetOpcode()) {
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case IR::Opcode::ImageSampleImplicitLod:
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return 2;
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case IR::Opcode::ImageSampleDrefImplicitLod:
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return 3;
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default:
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break;
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}
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return inst_info.is_depth ? 5 : 4;
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}();
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inst.SetArg(arg_pos, arg);
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}
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if (inst_info.explicit_lod) {
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ASSERT(inst.GetOpcode() == IR::Opcode::ImageFetch ||
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inst.GetOpcode() == IR::Opcode::ImageSampleExplicitLod ||
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inst.GetOpcode() == IR::Opcode::ImageSampleDrefExplicitLod);
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const u32 pos = inst.GetOpcode() == IR::Opcode::ImageSampleExplicitLod ? 2 : 3;
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const IR::Value value = inst_info.force_level0 ? ir.Imm32(0.f) : arg;
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inst.SetArg(pos, value);
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if (inst_info.has_lod) {
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ASSERT(inst.GetOpcode() == IR::Opcode::ImageFetch);
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inst.SetArg(3, arg);
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}
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}
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