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Misc fixes

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This commit is contained in:
Marcin Mikołajczyk 2025-06-29 15:18:00 +01:00
parent 7f727340aa
commit ecd73ebd67
3 changed files with 19 additions and 10 deletions
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9
src/shader_recompiler/frontend/copy_shader.cpp
View file

@ -14,7 +14,7 @@ CopyShaderData ParseCopyShader(std::span<const u32> code) {
constexpr u32 token_mov_vcchi = 0xBEEB03FF;
ASSERT_MSG(code[0] == token_mov_vcchi, "First instruction is not s_mov_b32 vcc_hi, #imm");
std::array<s32, 32> offsets{};
std::array<s32, 64> offsets{};
offsets.fill(-1);
std::array<s32, 256> sources{};
@ -52,6 +52,8 @@ CopyShaderData ParseCopyShader(std::span<const u32> code) {
break;
}
case Gcn::Opcode::BUFFER_LOAD_DWORD: {
ASSERT_MSG(inst.src[1].code < offsets.size(),
"offsets array for geometry shaders is too short");
offsets[inst.src[1].code] = inst.control.mubuf.offset;
if (inst.src[3].field != Gcn::OperandField::ConstZero) {
const u32 index = inst.src[3].code;
@ -66,7 +68,10 @@ CopyShaderData ParseCopyShader(std::span<const u32> code) {
}
if (last_attr != IR::Attribute::Position0) {
data.num_attrs = static_cast<u32>(last_attr) - static_cast<u32>(IR::Attribute::Param0) + 1;
data.num_attrs =
last_attr >= IR::Attribute::Param0
? static_cast<u32>(last_attr) - static_cast<u32>(IR::Attribute::Param0) + 1
: 0;
const auto it = data.attr_map.begin();
const u32 comp_stride = std::next(it)->first - it->first;
data.output_vertices = comp_stride / 64;

18
src/shader_recompiler/ir/passes/ring_access_elimination.cpp
View file

@ -142,14 +142,18 @@ void RingAccessElimination(const IR::Program& program, const RuntimeInfo& runtim
const auto vc_read_ofs = (((offset / comp_ofs) * comp_ofs) % output_size) * 16u;
const auto& it = info.gs_copy_data.attr_map.find(vc_read_ofs);
ASSERT(it != info.gs_copy_data.attr_map.cend());
const auto& [attr, comp] = it->second;
if (it == info.gs_copy_data.attr_map.cend()) {
LOG_ERROR(Render_Recompiler, "attr_map missing entry: {}", vc_read_ofs);
inst.Invalidate();
} else {
const auto& [attr, comp] = it->second;
inst.ReplaceOpcode(IR::Opcode::SetAttribute);
inst.ClearArgs();
inst.SetArg(0, IR::Value{attr});
inst.SetArg(1, data);
inst.SetArg(2, ir.Imm32(comp));
inst.ReplaceOpcode(IR::Opcode::SetAttribute);
inst.ClearArgs();
inst.SetArg(0, IR::Value{attr});
inst.SetArg(1, data);
inst.SetArg(2, ir.Imm32(comp));
}
break;
}
default:

2
src/video_core/amdgpu/pm4_cmds.h
View file

@ -699,7 +699,7 @@ struct PM4CmdWaitRegMem {
struct PM4CmdWriteData {
PM4Type3Header header;
union {
BitField<8, 11, u32> dst_sel;
BitField<8, 4, u32> dst_sel;
BitField<16, 1, u32> wr_one_addr;
BitField<20, 1, u32> wr_confirm;
BitField<30, 1, u32> engine_sel;