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https://github.com/shadps4-emu/shadPS4.git
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shader_recompiler: Implement render target swizzles when no format is available (#739)
* shader_recompiler: Use null image when shader is compiled with unbound sharp * video_core: Refactor and render target swizzles * liverpool_to_vk: Add missing swap format from RDR * video_core: Refactor shader recompiler interface * Makes it much easier to pass runtime information to the recompiler and have it treated as part of the shader key. Also pulls out most runtime state from Info struct * shader_recompiler: Avoid some asserts
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TheTurtle
GitHub
parent
3f8a8d3a24
commit
f087f43736
30 changed files with 704 additions and 560 deletions
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@ -602,13 +602,14 @@ public:
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Common::ObjectPool<IR::Block>& block_pool_,
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Common::ObjectPool<Statement>& stmt_pool_, Statement& root_stmt,
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IR::AbstractSyntaxList& syntax_list_, std::span<const GcnInst> inst_list_,
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Info& info_, const Profile& profile_)
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Info& info_, const RuntimeInfo& runtime_info_, const Profile& profile_)
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: stmt_pool{stmt_pool_}, inst_pool{inst_pool_}, block_pool{block_pool_},
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syntax_list{syntax_list_}, inst_list{inst_list_}, info{info_}, profile{profile_} {
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syntax_list{syntax_list_}, inst_list{inst_list_}, info{info_},
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runtime_info{runtime_info_}, profile{profile_} {
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Visit(root_stmt, nullptr, nullptr);
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IR::Block& first_block{*syntax_list.front().data.block};
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Translator{&first_block, info, profile}.EmitPrologue();
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Translator{&first_block, info, runtime_info, profile}.EmitPrologue();
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}
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private:
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@ -637,7 +638,7 @@ private:
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const u32 start = stmt.block->begin_index;
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const u32 size = stmt.block->end_index - start + 1;
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Translate(current_block, stmt.block->begin, inst_list.subspan(start, size),
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info, profile);
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info, runtime_info, profile);
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}
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break;
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}
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@ -817,19 +818,20 @@ private:
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const Block dummy_flow_block{.is_dummy = true};
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std::span<const GcnInst> inst_list;
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Info& info;
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const RuntimeInfo& runtime_info;
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const Profile& profile;
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};
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} // Anonymous namespace
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IR::AbstractSyntaxList BuildASL(Common::ObjectPool<IR::Inst>& inst_pool,
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Common::ObjectPool<IR::Block>& block_pool, CFG& cfg, Info& info,
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const Profile& profile) {
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const RuntimeInfo& runtime_info, const Profile& profile) {
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Common::ObjectPool<Statement> stmt_pool{64};
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GotoPass goto_pass{cfg, stmt_pool};
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Statement& root{goto_pass.RootStatement()};
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IR::AbstractSyntaxList syntax_list;
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TranslatePass{inst_pool, block_pool, stmt_pool, root,
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syntax_list, cfg.inst_list, info, profile};
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TranslatePass{inst_pool, block_pool, stmt_pool, root, syntax_list,
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cfg.inst_list, info, runtime_info, profile};
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ASSERT_MSG(!info.translation_failed, "Shader translation has failed");
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return syntax_list;
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}
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@ -11,12 +11,14 @@
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namespace Shader {
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struct Info;
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struct Profile;
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struct RuntimeInfo;
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} // namespace Shader
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namespace Shader::Gcn {
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[[nodiscard]] IR::AbstractSyntaxList BuildASL(Common::ObjectPool<IR::Inst>& inst_pool,
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Common::ObjectPool<IR::Block>& block_pool, CFG& cfg,
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Info& info, const Profile& profile);
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Info& info, const RuntimeInfo& runtime_info,
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const Profile& profile);
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} // namespace Shader::Gcn
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@ -2,6 +2,7 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/runtime_info.h"
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namespace Shader::Gcn {
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@ -19,12 +20,28 @@ void Translator::EmitExport(const GcnInst& inst) {
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IR::VectorReg(inst.src[3].code),
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};
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const auto swizzle = [&](u32 comp) {
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if (!IR::IsMrt(attrib)) {
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return comp;
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}
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const u32 index = u32(attrib) - u32(IR::Attribute::RenderTarget0);
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switch (runtime_info.fs_info.mrt_swizzles[index]) {
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case MrtSwizzle::Identity:
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return comp;
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case MrtSwizzle::Alt:
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static constexpr std::array<u32, 4> AltSwizzle = {2, 1, 0, 3};
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return AltSwizzle[comp];
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default:
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UNREACHABLE();
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}
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};
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const auto unpack = [&](u32 idx) {
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const IR::Value value = ir.UnpackHalf2x16(ir.GetVectorReg(vsrc[idx]));
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const IR::F32 r = IR::F32{ir.CompositeExtract(value, 0)};
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const IR::F32 g = IR::F32{ir.CompositeExtract(value, 1)};
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ir.SetAttribute(attrib, r, idx * 2);
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ir.SetAttribute(attrib, g, idx * 2 + 1);
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ir.SetAttribute(attrib, r, swizzle(idx * 2));
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ir.SetAttribute(attrib, g, swizzle(idx * 2 + 1));
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};
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// Components are float16 packed into a VGPR
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@ -45,7 +62,7 @@ void Translator::EmitExport(const GcnInst& inst) {
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continue;
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}
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const IR::F32 comp = ir.GetVectorReg<IR::F32>(vsrc[i]);
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ir.SetAttribute(attrib, comp, i);
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ir.SetAttribute(attrib, comp, swizzle(i));
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}
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}
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}
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@ -7,6 +7,7 @@
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/fetch_shader.h"
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/info.h"
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#include "shader_recompiler/runtime_info.h"
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#include "video_core/amdgpu/resource.h"
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@ -16,8 +17,9 @@
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namespace Shader::Gcn {
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Translator::Translator(IR::Block* block_, Info& info_, const Profile& profile_)
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: ir{*block_, block_->begin()}, info{info_}, profile{profile_} {}
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Translator::Translator(IR::Block* block_, Info& info_, const RuntimeInfo& runtime_info_,
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const Profile& profile_)
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: ir{*block_, block_->begin()}, info{info_}, runtime_info{runtime_info_}, profile{profile_} {}
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void Translator::EmitPrologue() {
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ir.Prologue();
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@ -25,7 +27,7 @@ void Translator::EmitPrologue() {
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// Initialize user data.
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IR::ScalarReg dst_sreg = IR::ScalarReg::S0;
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for (u32 i = 0; i < info.num_user_data; i++) {
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for (u32 i = 0; i < runtime_info.num_user_data; i++) {
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ir.SetScalarReg(dst_sreg, ir.GetUserData(dst_sreg));
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++dst_sreg;
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}
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@ -36,15 +38,15 @@ void Translator::EmitPrologue() {
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// v0: vertex ID, always present
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::VertexId));
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// v1: instance ID, step rate 0
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if (info.num_input_vgprs > 0) {
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if (runtime_info.num_input_vgprs > 0) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId0));
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}
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// v2: instance ID, step rate 1
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if (info.num_input_vgprs > 1) {
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if (runtime_info.num_input_vgprs > 1) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId1));
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}
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// v3: instance ID, plain
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if (info.num_input_vgprs > 2) {
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if (runtime_info.num_input_vgprs > 2) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId));
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}
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break;
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@ -64,13 +66,13 @@ void Translator::EmitPrologue() {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 1));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 2));
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if (info.tgid_enable[0]) {
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if (runtime_info.cs_info.tgid_enable[0]) {
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 0));
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}
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if (info.tgid_enable[1]) {
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if (runtime_info.cs_info.tgid_enable[1]) {
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 1));
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}
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if (info.tgid_enable[2]) {
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if (runtime_info.cs_info.tgid_enable[2]) {
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 2));
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}
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break;
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@ -445,7 +447,6 @@ void Translator::EmitFlowControl(u32 pc, const GcnInst& inst) {
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}
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void Translator::LogMissingOpcode(const GcnInst& inst) {
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const u32 opcode = u32(inst.opcode);
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LOG_ERROR(Render_Recompiler, "Unknown opcode {} ({}, category = {})",
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magic_enum::enum_name(inst.opcode), u32(inst.opcode),
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magic_enum::enum_name(inst.category));
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@ -453,11 +454,11 @@ void Translator::LogMissingOpcode(const GcnInst& inst) {
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}
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void Translate(IR::Block* block, u32 pc, std::span<const GcnInst> inst_list, Info& info,
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const Profile& profile) {
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const RuntimeInfo& runtime_info, const Profile& profile) {
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if (inst_list.empty()) {
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return;
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}
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Translator translator{block, info, profile};
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Translator translator{block, info, runtime_info, profile};
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for (const auto& inst : inst_list) {
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pc += inst.length;
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@ -5,9 +5,9 @@
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#include <span>
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#include "shader_recompiler/frontend/instruction.h"
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#include "shader_recompiler/info.h"
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#include "shader_recompiler/ir/basic_block.h"
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#include "shader_recompiler/ir/ir_emitter.h"
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#include "shader_recompiler/runtime_info.h"
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namespace Shader {
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struct Info;
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@ -55,7 +55,8 @@ enum class NegateMode : u32 {
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class Translator {
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public:
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explicit Translator(IR::Block* block_, Info& info, const Profile& profile);
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explicit Translator(IR::Block* block_, Info& info, const RuntimeInfo& runtime_info,
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const Profile& profile);
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// Instruction categories
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void EmitPrologue();
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@ -237,12 +238,13 @@ private:
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private:
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IR::IREmitter ir;
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Info& info;
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const RuntimeInfo& runtime_info;
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const Profile& profile;
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IR::U32 m0_value;
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bool opcode_missing = false;
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};
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void Translate(IR::Block* block, u32 block_base, std::span<const GcnInst> inst_list, Info& info,
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const Profile& profile);
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const RuntimeInfo& runtime_info, const Profile& profile);
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} // namespace Shader::Gcn
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@ -479,10 +479,11 @@ void Translator::V_ADD_F32(const GcnInst& inst) {
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void Translator::V_CVT_OFF_F32_I4(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::VectorReg dst_reg{inst.dst[0].code};
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ir.SetVectorReg(
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dst_reg,
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ir.FPMul(ir.ConvertUToF(32, 32, ir.ISub(ir.BitwiseAnd(src0, ir.Imm32(0xF)), ir.Imm32(8))),
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ir.Imm32(1.f / 16.f)));
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ASSERT(src0.IsImmediate());
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static constexpr std::array IntToFloat = {
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0.0f, 0.0625f, 0.1250f, 0.1875f, 0.2500f, 0.3125f, 0.3750f, 0.4375f,
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-0.5000f, -0.4375f, -0.3750f, -0.3125f, -0.2500f, -0.1875f, -0.1250f, -0.0625f};
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ir.SetVectorReg(dst_reg, ir.Imm32(IntToFloat[src0.U32()]));
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}
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void Translator::V_MED3_F32(const GcnInst& inst) {
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@ -7,14 +7,14 @@ namespace Shader::Gcn {
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void Translator::V_INTERP_P2_F32(const GcnInst& inst) {
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const IR::VectorReg dst_reg{inst.dst[0].code};
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auto& attr = info.ps_inputs.at(inst.control.vintrp.attr);
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auto& attr = runtime_info.fs_info.inputs.at(inst.control.vintrp.attr);
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const IR::Attribute attrib{IR::Attribute::Param0 + attr.param_index};
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ir.SetVectorReg(dst_reg, ir.GetAttribute(attrib, inst.control.vintrp.chan));
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}
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void Translator::V_INTERP_MOV_F32(const GcnInst& inst) {
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const IR::VectorReg dst_reg{inst.dst[0].code};
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auto& attr = info.ps_inputs.at(inst.control.vintrp.attr);
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auto& attr = runtime_info.fs_info.inputs.at(inst.control.vintrp.attr);
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const IR::Attribute attrib{IR::Attribute::Param0 + attr.param_index};
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ir.SetVectorReg(dst_reg, ir.GetAttribute(attrib, inst.control.vintrp.chan));
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}
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