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Use IAddCarry instead

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offtkp 2025-07-06 23:09:51 +03:00
parent 0845fe2b2b
commit f90ff7769f
1 changed files with 8 additions and 6 deletions
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14
src/shader_recompiler/frontend/translate/vector_alu.cpp
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@ -623,13 +623,15 @@ void Translator::V_ADDC_U32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
const IR::U32 carry{GetCarryIn(inst)};
const IR::U32 temp{ir.IAdd(src0, src1)};
const IR::U32 result{ir.IAdd(temp, carry)};
SetDst(inst.dst[0], result);
const IR::Value tmp1{ir.IAddCary(src0, src1)};
const IR::U32 result1{ir.CompositeExtract(tmp1, 0)};
const IR::U32 carry_out1{ir.CompositeExtract(tmp1, 1)};
const IR::Value tmp2{ir.IAddCary(result1, carry)};
const IR::U32 result2{ir.CompositeExtract(tmp2, 0)};
const IR::U32 carry_out2{ir.CompositeExtract(tmp2, 1)};
SetDst(inst.dst[0], result2);
const IR::U1 less_1{ir.ILessThan(temp, src0, false)};
const IR::U1 less_2{ir.ILessThan(result, carry, false)};
const IR::U1 did_overflow{ir.LogicalOr(less_1, less_2)};
const IR::U1 did_overflow{ir.INotEqual(ir.BitwiseOr(carry_out1, carry_out2), ir.Imm32(0))};
SetCarryOut(inst, did_overflow);
}