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https://github.com/shadps4-emu/shadPS4.git
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Implemented load_buffer_format_* conversions (#295)
* Implemented load_buffer_format_* conversions * clang-format insists on ugly things
This commit is contained in:
Vladislav Mikhalin
GitHub
parent
c6cdfcfb0b
commit
f9e96793cc
15 changed files with 475 additions and 91 deletions
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@ -4,6 +4,8 @@
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#include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
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#include "shader_recompiler/backend/spirv/spirv_emit_context.h"
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#include <magic_enum.hpp>
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namespace Shader::Backend::SPIRV {
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namespace {
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@ -209,57 +211,216 @@ void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, u32 elemen
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ctx.OpStore(pointer, value);
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}
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Id EmitLoadBufferF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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const auto info = inst->Flags<IR::BufferInstInfo>();
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const auto& buffer = ctx.buffers[handle];
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if (info.index_enable && info.offset_enable) {
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UNREACHABLE();
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} else if (info.index_enable) {
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const Id ptr{
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ctx.OpAccessChain(buffer.pointer_type, buffer.id, ctx.u32_zero_value, address)};
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return ctx.OpLoad(buffer.data_types->Get(1), ptr);
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}
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UNREACHABLE();
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}
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Id EmitLoadBufferU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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return EmitLoadBufferF32(ctx, inst, handle, address);
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}
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Id EmitLoadBufferF32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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const auto info = inst->Flags<IR::BufferInstInfo>();
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template <int N>
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static Id EmitLoadBufferF32xN(EmitContext& ctx, u32 handle, Id address) {
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const auto& buffer = ctx.buffers[handle];
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boost::container::static_vector<Id, 2> ids;
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for (u32 i = 0; i < 2; i++) {
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const Id index{ctx.OpIAdd(ctx.U32[1], address, ctx.ConstU32(i))};
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const Id ptr{ctx.OpAccessChain(buffer.pointer_type, buffer.id, ctx.u32_zero_value, index)};
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ids.push_back(ctx.OpLoad(buffer.data_types->Get(1), ptr));
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Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(2u));
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if constexpr (N == 1) {
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const Id ptr{
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ctx.OpAccessChain(buffer.pointer_type, buffer.id, ctx.u32_zero_value, address)};
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return ctx.OpLoad(buffer.data_types->Get(1), ptr);
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} else {
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boost::container::static_vector<Id, N> ids;
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for (u32 i = 0; i < N; i++) {
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index = ctx.OpIAdd(ctx.U32[1], index, ctx.ConstU32(i));
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const Id ptr{
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ctx.OpAccessChain(buffer.pointer_type, buffer.id, ctx.u32_zero_value, index)};
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ids.push_back(ctx.OpLoad(buffer.data_types->Get(1), ptr));
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}
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return ctx.OpCompositeConstruct(buffer.data_types->Get(N), ids);
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}
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return ctx.OpCompositeConstruct(buffer.data_types->Get(2), ids);
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}
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Id EmitLoadBufferF32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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const auto info = inst->Flags<IR::BufferInstInfo>();
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const auto& buffer = ctx.buffers[handle];
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boost::container::static_vector<Id, 3> ids;
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for (u32 i = 0; i < 3; i++) {
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const Id index{ctx.OpIAdd(ctx.U32[1], address, ctx.ConstU32(i))};
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const Id ptr{ctx.OpAccessChain(buffer.pointer_type, buffer.id, ctx.u32_zero_value, index)};
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ids.push_back(ctx.OpLoad(buffer.data_types->Get(1), ptr));
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}
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return ctx.OpCompositeConstruct(buffer.data_types->Get(3), ids);
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Id EmitLoadBufferF32(EmitContext& ctx, IR::Inst*, u32 handle, Id address) {
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return EmitLoadBufferF32xN<1>(ctx, handle, address);
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}
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Id EmitLoadBufferF32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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const auto info = inst->Flags<IR::BufferInstInfo>();
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const auto& buffer = ctx.buffers[handle];
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boost::container::static_vector<Id, 4> ids;
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for (u32 i = 0; i < 4; i++) {
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const Id index{ctx.OpIAdd(ctx.U32[1], address, ctx.ConstU32(i))};
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const Id ptr{ctx.OpAccessChain(buffer.pointer_type, buffer.id, ctx.u32_zero_value, index)};
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ids.push_back(ctx.OpLoad(buffer.data_types->Get(1), ptr));
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Id EmitLoadBufferF32x2(EmitContext& ctx, IR::Inst*, u32 handle, Id address) {
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return EmitLoadBufferF32xN<2>(ctx, handle, address);
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}
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Id EmitLoadBufferF32x3(EmitContext& ctx, IR::Inst*, u32 handle, Id address) {
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return EmitLoadBufferF32xN<3>(ctx, handle, address);
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}
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Id EmitLoadBufferF32x4(EmitContext& ctx, IR::Inst*, u32 handle, Id address) {
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return EmitLoadBufferF32xN<4>(ctx, handle, address);
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}
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static bool IsSignedInteger(AmdGpu::NumberFormat format) {
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switch (format) {
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case AmdGpu::NumberFormat::Unorm:
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case AmdGpu::NumberFormat::Uscaled:
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case AmdGpu::NumberFormat::Uint:
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return false;
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case AmdGpu::NumberFormat::Snorm:
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case AmdGpu::NumberFormat::Sscaled:
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case AmdGpu::NumberFormat::Sint:
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case AmdGpu::NumberFormat::SnormNz:
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return true;
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case AmdGpu::NumberFormat::Float:
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default:
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UNREACHABLE();
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}
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return ctx.OpCompositeConstruct(buffer.data_types->Get(4), ids);
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}
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static u32 UXBitsMax(u32 bit_width) {
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return (1u << bit_width) - 1u;
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}
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static u32 SXBitsMax(u32 bit_width) {
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return (1u << (bit_width - 1u)) - 1u;
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}
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static Id ConvertValue(EmitContext& ctx, Id value, AmdGpu::NumberFormat format, u32 bit_width) {
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switch (format) {
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case AmdGpu::NumberFormat::Unorm:
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return ctx.OpFDiv(ctx.F32[1], value, ctx.ConstF32(float(UXBitsMax(bit_width))));
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case AmdGpu::NumberFormat::Snorm:
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return ctx.OpFDiv(ctx.F32[1], value, ctx.ConstF32(float(SXBitsMax(bit_width))));
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case AmdGpu::NumberFormat::SnormNz:
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// (x * 2 + 1) / (Format::SMAX * 2)
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value = ctx.OpFMul(ctx.F32[1], value, ctx.ConstF32(2.f));
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value = ctx.OpFAdd(ctx.F32[1], value, ctx.ConstF32(1.f));
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return ctx.OpFDiv(ctx.F32[1], value, ctx.ConstF32(float(SXBitsMax(bit_width) * 2)));
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case AmdGpu::NumberFormat::Uscaled:
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case AmdGpu::NumberFormat::Sscaled:
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case AmdGpu::NumberFormat::Uint:
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case AmdGpu::NumberFormat::Sint:
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case AmdGpu::NumberFormat::Float:
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return value;
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default:
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UNREACHABLE_MSG("Unsupported number fromat for conversion: {}",
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magic_enum::enum_name(format));
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}
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}
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static Id ComponentOffset(EmitContext& ctx, Id address, u32 stride, u32 bit_offset) {
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Id comp_offset = ctx.ConstU32(bit_offset);
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if (stride < 4) {
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// comp_offset += (address % 4) * 8;
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const Id byte_offset = ctx.OpUMod(ctx.U32[1], address, ctx.ConstU32(4u));
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const Id bit_offset = ctx.OpShiftLeftLogical(ctx.U32[1], byte_offset, ctx.ConstU32(3u));
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comp_offset = ctx.OpIAdd(ctx.U32[1], comp_offset, bit_offset);
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}
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return comp_offset;
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}
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static Id GetBufferFormatValue(EmitContext& ctx, u32 handle, Id address, u32 comp) {
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const auto& buffer = ctx.buffers[handle];
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const auto format = buffer.buffer.GetDataFmt();
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switch (format) {
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case AmdGpu::DataFormat::FormatInvalid:
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return ctx.f32_zero_value;
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case AmdGpu::DataFormat::Format8:
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case AmdGpu::DataFormat::Format16:
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case AmdGpu::DataFormat::Format32:
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case AmdGpu::DataFormat::Format8_8:
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case AmdGpu::DataFormat::Format16_16:
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case AmdGpu::DataFormat::Format10_11_11:
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case AmdGpu::DataFormat::Format11_11_10:
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case AmdGpu::DataFormat::Format10_10_10_2:
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case AmdGpu::DataFormat::Format2_10_10_10:
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case AmdGpu::DataFormat::Format8_8_8_8:
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case AmdGpu::DataFormat::Format32_32:
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case AmdGpu::DataFormat::Format16_16_16_16:
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case AmdGpu::DataFormat::Format32_32_32:
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case AmdGpu::DataFormat::Format32_32_32_32: {
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const u32 num_components = AmdGpu::NumComponents(format);
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if (comp >= num_components) {
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return ctx.f32_zero_value;
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}
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// uint index = address / 4;
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Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(2u));
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const u32 stride = buffer.buffer.GetStride();
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if (stride > 4) {
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const u32 index_offset = u32(AmdGpu::ComponentOffset(format, comp) / 32);
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if (index_offset > 0) {
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// index += index_offset;
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index = ctx.OpIAdd(ctx.U32[1], index, ctx.ConstU32(index_offset));
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}
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}
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const Id ptr = ctx.OpAccessChain(buffer.pointer_type, buffer.id, ctx.u32_zero_value, index);
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const u32 bit_offset = AmdGpu::ComponentOffset(format, comp) % 32;
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const u32 bit_width = AmdGpu::ComponentBits(format, comp);
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const auto num_format = buffer.buffer.GetNumberFmt();
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if (num_format == AmdGpu::NumberFormat::Float) {
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if (bit_width == 32) {
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return ctx.OpLoad(ctx.F32[1], ptr);
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} else if (bit_width == 16) {
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const Id comp_offset = ComponentOffset(ctx, address, stride, bit_offset);
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Id value = ctx.OpLoad(ctx.U32[1], ptr);
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value =
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ctx.OpBitFieldSExtract(ctx.S32[1], value, comp_offset, ctx.ConstU32(bit_width));
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value = ctx.OpSConvert(ctx.U16, value);
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value = ctx.OpBitcast(ctx.F16[1], value);
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return ctx.OpFConvert(ctx.F32[1], value);
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} else {
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UNREACHABLE_MSG("Invalid float bit width {}", bit_width);
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}
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} else {
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Id value = ctx.OpLoad(ctx.U32[1], ptr);
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const bool is_signed = IsSignedInteger(num_format);
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if (bit_width < 32) {
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const Id comp_offset = ComponentOffset(ctx, address, stride, bit_offset);
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if (is_signed) {
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value = ctx.OpBitFieldSExtract(ctx.S32[1], value, comp_offset,
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ctx.ConstU32(bit_width));
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value = ctx.OpConvertSToF(ctx.F32[1], value);
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} else {
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value = ctx.OpBitFieldUExtract(ctx.U32[1], value, comp_offset,
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ctx.ConstU32(bit_width));
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value = ctx.OpConvertUToF(ctx.F32[1], value);
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}
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} else {
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if (is_signed) {
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value = ctx.OpConvertSToF(ctx.F32[1], value);
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} else {
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value = ctx.OpConvertUToF(ctx.F32[1], value);
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}
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}
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return ConvertValue(ctx, value, num_format, bit_width);
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}
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break;
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}
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default:
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UNREACHABLE_MSG("Invalid format for conversion: {}", magic_enum::enum_name(format));
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}
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}
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template <int N>
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static Id EmitLoadBufferFormatF32xN(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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if constexpr (N == 1) {
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return GetBufferFormatValue(ctx, handle, address, 0);
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} else {
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boost::container::static_vector<Id, N> ids;
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for (u32 i = 0; i < N; i++) {
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ids.push_back(GetBufferFormatValue(ctx, handle, address, i));
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}
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return ctx.OpCompositeConstruct(ctx.F32[N], ids);
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}
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}
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Id EmitLoadBufferFormatF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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return EmitLoadBufferFormatF32xN<1>(ctx, inst, handle, address);
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}
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Id EmitLoadBufferFormatF32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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return EmitLoadBufferFormatF32xN<2>(ctx, inst, handle, address);
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}
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Id EmitLoadBufferFormatF32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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return EmitLoadBufferFormatF32xN<3>(ctx, inst, handle, address);
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}
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Id EmitLoadBufferFormatF32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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return EmitLoadBufferFormatF32xN<4>(ctx, inst, handle, address);
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}
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void EmitStoreBufferF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
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@ -66,6 +66,10 @@ Id EmitLoadBufferF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
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Id EmitLoadBufferF32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
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Id EmitLoadBufferF32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
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Id EmitLoadBufferF32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
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Id EmitLoadBufferFormatF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
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Id EmitLoadBufferFormatF32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
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Id EmitLoadBufferFormatF32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
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Id EmitLoadBufferFormatF32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
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Id EmitLoadBufferU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address);
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void EmitStoreBufferF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
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void EmitStoreBufferF32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
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@ -301,9 +301,7 @@ void EmitContext::DefineBuffers(const Info& info) {
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for (u32 i = 0; const auto& buffer : info.buffers) {
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const auto* data_types = True(buffer.used_types & IR::Type::F32) ? &F32 : &U32;
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const Id data_type = (*data_types)[1];
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const u32 stride = buffer.stride == 0 ? 1 : buffer.stride;
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const u32 num_elements = stride * buffer.num_records;
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const Id record_array_type{TypeArray(data_type, ConstU32(num_elements))};
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const Id record_array_type{TypeArray(data_type, ConstU32(buffer.length))};
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const Id struct_type{TypeStruct(record_array_type)};
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if (std::ranges::find(type_ids, record_array_type.value, &Id::value) == type_ids.end()) {
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Decorate(record_array_type, spv::Decoration::ArrayStride, 4);
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@ -333,6 +331,7 @@ void EmitContext::DefineBuffers(const Info& info) {
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.id = id,
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.data_types = data_types,
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.pointer_type = pointer_type,
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.buffer = buffer.GetVsharp(info),
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});
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interfaces.push_back(id);
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i++;
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@ -201,6 +201,7 @@ public:
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Id id;
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const VectorIds* data_types;
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Id pointer_type;
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AmdGpu::Buffer buffer;
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};
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u32& binding;
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