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* buffer_atomic_imax_x2 * Define Int64Atomics SPIR-V capability
533 lines
21 KiB
C++
533 lines
21 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <span>
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#include <type_traits>
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#include <utility>
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#include <vector>
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#include "common/assert.h"
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#include "common/func_traits.h"
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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#include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
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#include "shader_recompiler/backend/spirv/spirv_emit_context.h"
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/ir/basic_block.h"
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#include "shader_recompiler/ir/program.h"
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#include "shader_recompiler/runtime_info.h"
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#include "video_core/amdgpu/types.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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static constexpr spv::ExecutionMode GetInputPrimitiveType(AmdGpu::PrimitiveType type) {
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switch (type) {
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case AmdGpu::PrimitiveType::PointList:
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return spv::ExecutionMode::InputPoints;
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case AmdGpu::PrimitiveType::LineList:
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case AmdGpu::PrimitiveType::LineStrip:
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return spv::ExecutionMode::InputLines;
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case AmdGpu::PrimitiveType::TriangleList:
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case AmdGpu::PrimitiveType::TriangleStrip:
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case AmdGpu::PrimitiveType::RectList:
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return spv::ExecutionMode::Triangles;
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case AmdGpu::PrimitiveType::AdjTriangleList:
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return spv::ExecutionMode::InputTrianglesAdjacency;
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case AmdGpu::PrimitiveType::AdjLineList:
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return spv::ExecutionMode::InputLinesAdjacency;
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default:
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UNREACHABLE_MSG("Unknown input primitive type {}", u32(type));
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}
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}
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static constexpr spv::ExecutionMode GetOutputPrimitiveType(AmdGpu::GsOutputPrimitiveType type) {
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switch (type) {
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case AmdGpu::GsOutputPrimitiveType::PointList:
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return spv::ExecutionMode::OutputVertices;
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case AmdGpu::GsOutputPrimitiveType::LineStrip:
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return spv::ExecutionMode::OutputLineStrip;
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case AmdGpu::GsOutputPrimitiveType::TriangleStrip:
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return spv::ExecutionMode::OutputTriangleStrip;
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default:
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UNREACHABLE_MSG("Unknown output primitive type {}", u32(type));
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}
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}
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template <auto func, typename... Args>
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void SetDefinition(EmitContext& ctx, IR::Inst* inst, Args... args) {
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inst->SetDefinition<Id>(func(ctx, std::forward<Args>(args)...));
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}
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template <typename ArgType>
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ArgType Arg(EmitContext& ctx, const IR::Value& arg) {
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if constexpr (std::is_same_v<ArgType, Id>) {
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return ctx.Def(arg);
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} else if constexpr (std::is_same_v<ArgType, const IR::Value&>) {
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return arg;
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} else if constexpr (std::is_same_v<ArgType, u32>) {
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return arg.U32();
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} else if constexpr (std::is_same_v<ArgType, u64>) {
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return arg.U64();
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} else if constexpr (std::is_same_v<ArgType, bool>) {
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return arg.U1();
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} else if constexpr (std::is_same_v<ArgType, IR::Attribute>) {
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return arg.Attribute();
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} else if constexpr (std::is_same_v<ArgType, IR::ScalarReg>) {
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return arg.ScalarReg();
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} else if constexpr (std::is_same_v<ArgType, IR::VectorReg>) {
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return arg.VectorReg();
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} else if constexpr (std::is_same_v<ArgType, const char*>) {
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return arg.StringLiteral();
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} else if constexpr (std::is_same_v<ArgType, IR::Patch>) {
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return arg.Patch();
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}
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UNREACHABLE();
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}
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template <auto func, bool is_first_arg_inst, size_t... I>
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void Invoke(EmitContext& ctx, IR::Inst* inst, std::index_sequence<I...>) {
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using Traits = Common::FuncTraits<decltype(func)>;
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if constexpr (std::is_same_v<typename Traits::ReturnType, Id>) {
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if constexpr (is_first_arg_inst) {
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SetDefinition<func>(
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ctx, inst, inst,
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Arg<typename Traits::template ArgType<I + 2>>(ctx, inst->Arg(I))...);
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} else {
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SetDefinition<func>(
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ctx, inst, Arg<typename Traits::template ArgType<I + 1>>(ctx, inst->Arg(I))...);
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}
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} else {
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if constexpr (is_first_arg_inst) {
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func(ctx, inst, Arg<typename Traits::template ArgType<I + 2>>(ctx, inst->Arg(I))...);
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} else {
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func(ctx, Arg<typename Traits::template ArgType<I + 1>>(ctx, inst->Arg(I))...);
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}
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}
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}
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template <auto func>
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void Invoke(EmitContext& ctx, IR::Inst* inst) {
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using Traits = Common::FuncTraits<decltype(func)>;
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static_assert(Traits::NUM_ARGS >= 1, "Insufficient arguments");
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if constexpr (Traits::NUM_ARGS == 1) {
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Invoke<func, false>(ctx, inst, std::make_index_sequence<0>{});
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} else {
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using FirstArgType = typename Traits::template ArgType<1>;
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static constexpr bool is_first_arg_inst = std::is_same_v<FirstArgType, IR::Inst*>;
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using Indices = std::make_index_sequence<Traits::NUM_ARGS - (is_first_arg_inst ? 2 : 1)>;
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Invoke<func, is_first_arg_inst>(ctx, inst, Indices{});
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}
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}
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void EmitInst(EmitContext& ctx, IR::Inst* inst) {
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switch (inst->GetOpcode()) {
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#define OPCODE(name, result_type, ...) \
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case IR::Opcode::name: \
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return Invoke<&Emit##name>(ctx, inst);
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#include "shader_recompiler/ir/opcodes.inc"
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#undef OPCODE
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}
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UNREACHABLE_MSG("Invalid opcode {}", inst->GetOpcode());
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}
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Id TypeId(const EmitContext& ctx, IR::Type type) {
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switch (type) {
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case IR::Type::U1:
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return ctx.U1[1];
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case IR::Type::U32:
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return ctx.U32[1];
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default:
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throw NotImplementedException("Phi node type {}", type);
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}
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}
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void Traverse(EmitContext& ctx, const IR::Program& program) {
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IR::Block* current_block{};
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for (const IR::AbstractSyntaxNode& node : program.syntax_list) {
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switch (node.type) {
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case IR::AbstractSyntaxNode::Type::Block: {
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const Id label{node.data.block->Definition<Id>()};
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if (current_block) {
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ctx.OpBranch(label);
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}
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current_block = node.data.block;
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ctx.AddLabel(label);
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for (IR::Inst& inst : node.data.block->Instructions()) {
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EmitInst(ctx, &inst);
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}
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ctx.first_to_last_label_map[label.value] = ctx.last_label;
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break;
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}
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case IR::AbstractSyntaxNode::Type::If: {
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const Id if_label{node.data.if_node.body->Definition<Id>()};
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const Id endif_label{node.data.if_node.merge->Definition<Id>()};
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ctx.OpSelectionMerge(endif_label, spv::SelectionControlMask::MaskNone);
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ctx.OpBranchConditional(ctx.Def(node.data.if_node.cond), if_label, endif_label);
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break;
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}
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case IR::AbstractSyntaxNode::Type::Loop: {
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const Id body_label{node.data.loop.body->Definition<Id>()};
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const Id continue_label{node.data.loop.continue_block->Definition<Id>()};
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const Id endloop_label{node.data.loop.merge->Definition<Id>()};
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ctx.OpLoopMerge(endloop_label, continue_label, spv::LoopControlMask::MaskNone);
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ctx.OpBranch(body_label);
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break;
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}
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case IR::AbstractSyntaxNode::Type::Break: {
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const Id break_label{node.data.break_node.merge->Definition<Id>()};
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const Id skip_label{node.data.break_node.skip->Definition<Id>()};
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ctx.OpBranchConditional(ctx.Def(node.data.break_node.cond), break_label, skip_label);
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break;
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}
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case IR::AbstractSyntaxNode::Type::EndIf:
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if (current_block) {
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ctx.OpBranch(node.data.end_if.merge->Definition<Id>());
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}
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break;
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case IR::AbstractSyntaxNode::Type::Repeat: {
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Id cond{ctx.Def(node.data.repeat.cond)};
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const Id loop_header_label{node.data.repeat.loop_header->Definition<Id>()};
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const Id merge_label{node.data.repeat.merge->Definition<Id>()};
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ctx.OpBranchConditional(cond, loop_header_label, merge_label);
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break;
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}
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case IR::AbstractSyntaxNode::Type::Return:
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ctx.OpReturn();
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break;
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case IR::AbstractSyntaxNode::Type::Unreachable:
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ctx.OpUnreachable();
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break;
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}
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if (node.type != IR::AbstractSyntaxNode::Type::Block) {
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current_block = nullptr;
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}
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}
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}
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Id DefineMain(EmitContext& ctx, const IR::Program& program) {
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const Id void_function{ctx.TypeFunction(ctx.void_id)};
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const Id main{ctx.OpFunction(ctx.void_id, spv::FunctionControlMask::MaskNone, void_function)};
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for (IR::Block* const block : program.blocks) {
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block->SetDefinition(ctx.OpLabel());
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}
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Traverse(ctx, program);
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ctx.OpFunctionEnd();
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return main;
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}
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spv::ExecutionMode ExecutionMode(AmdGpu::TessellationType primitive) {
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switch (primitive) {
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case AmdGpu::TessellationType::Isoline:
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return spv::ExecutionMode::Isolines;
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case AmdGpu::TessellationType::Triangle:
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return spv::ExecutionMode::Triangles;
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case AmdGpu::TessellationType::Quad:
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return spv::ExecutionMode::Quads;
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}
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UNREACHABLE_MSG("Tessellation primitive {}", primitive);
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}
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spv::ExecutionMode ExecutionMode(AmdGpu::TessellationPartitioning spacing) {
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switch (spacing) {
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case AmdGpu::TessellationPartitioning::Integer:
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return spv::ExecutionMode::SpacingEqual;
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case AmdGpu::TessellationPartitioning::FracOdd:
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return spv::ExecutionMode::SpacingFractionalOdd;
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case AmdGpu::TessellationPartitioning::FracEven:
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return spv::ExecutionMode::SpacingFractionalEven;
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default:
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break;
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}
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UNREACHABLE_MSG("Tessellation spacing {}", spacing);
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}
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void SetupCapabilities(const Info& info, const Profile& profile, EmitContext& ctx) {
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ctx.AddCapability(spv::Capability::Image1D);
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ctx.AddCapability(spv::Capability::Sampled1D);
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ctx.AddCapability(spv::Capability::ImageQuery);
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ctx.AddCapability(spv::Capability::Int8);
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ctx.AddCapability(spv::Capability::Int16);
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ctx.AddCapability(spv::Capability::Int64);
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ctx.AddCapability(spv::Capability::UniformAndStorageBuffer8BitAccess);
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ctx.AddCapability(spv::Capability::UniformAndStorageBuffer16BitAccess);
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if (info.uses_fp16) {
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ctx.AddCapability(spv::Capability::Float16);
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}
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if (info.uses_fp64) {
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ctx.AddCapability(spv::Capability::Float64);
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}
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if (info.has_storage_images) {
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ctx.AddCapability(spv::Capability::StorageImageExtendedFormats);
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ctx.AddCapability(spv::Capability::StorageImageReadWithoutFormat);
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ctx.AddCapability(spv::Capability::StorageImageWriteWithoutFormat);
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if (profile.supports_image_load_store_lod) {
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ctx.AddExtension("SPV_AMD_shader_image_load_store_lod");
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ctx.AddCapability(spv::Capability::ImageReadWriteLodAMD);
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}
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}
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if (info.has_image_gather) {
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ctx.AddCapability(spv::Capability::ImageGatherExtended);
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}
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if (info.has_image_query) {
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ctx.AddCapability(spv::Capability::ImageQuery);
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}
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if ((info.uses_image_atomic_float_min_max && profile.supports_image_fp32_atomic_min_max) ||
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(info.uses_buffer_atomic_float_min_max && profile.supports_buffer_fp32_atomic_min_max)) {
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ctx.AddExtension("SPV_EXT_shader_atomic_float_min_max");
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ctx.AddCapability(spv::Capability::AtomicFloat32MinMaxEXT);
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}
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if (info.uses_lane_id) {
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ctx.AddCapability(spv::Capability::GroupNonUniform);
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}
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if (info.uses_group_quad) {
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ctx.AddCapability(spv::Capability::GroupNonUniformQuad);
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}
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if (info.uses_group_ballot) {
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ctx.AddCapability(spv::Capability::GroupNonUniformBallot);
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}
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const auto stage = info.l_stage;
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if (stage == LogicalStage::Vertex) {
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ctx.AddExtension("SPV_KHR_shader_draw_parameters");
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ctx.AddCapability(spv::Capability::DrawParameters);
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}
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if (stage == LogicalStage::Geometry) {
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ctx.AddCapability(spv::Capability::Geometry);
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}
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if (info.stage == Stage::Fragment && profile.needs_manual_interpolation) {
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ctx.AddExtension("SPV_KHR_fragment_shader_barycentric");
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ctx.AddCapability(spv::Capability::FragmentBarycentricKHR);
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}
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if (stage == LogicalStage::TessellationControl || stage == LogicalStage::TessellationEval) {
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ctx.AddCapability(spv::Capability::Tessellation);
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}
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if (info.uses_dma) {
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ctx.AddCapability(spv::Capability::PhysicalStorageBufferAddresses);
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ctx.AddExtension("SPV_KHR_physical_storage_buffer");
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}
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const auto shared_type_count = std::popcount(static_cast<u32>(info.shared_types));
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if (shared_type_count > 1 && profile.supports_workgroup_explicit_memory_layout) {
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ctx.AddExtension("SPV_KHR_workgroup_memory_explicit_layout");
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ctx.AddCapability(spv::Capability::WorkgroupMemoryExplicitLayoutKHR);
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ctx.AddCapability(spv::Capability::WorkgroupMemoryExplicitLayout16BitAccessKHR);
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}
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if (info.uses_buffer_int64_atomics || info.uses_shared_int64_atomics) {
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if (info.uses_buffer_int64_atomics) {
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ASSERT_MSG(ctx.profile.supports_buffer_int64_atomics,
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"Shader requires support for atomic Int64 buffer operations that your "
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"Vulkan instance does not advertise");
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}
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if (info.uses_shared_int64_atomics) {
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ASSERT_MSG(ctx.profile.supports_shared_int64_atomics,
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"Shader requires support for atomic Int64 shared memory operations that "
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"your Vulkan instance does not advertise");
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}
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ctx.AddCapability(spv::Capability::Int64Atomics);
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}
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}
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void DefineEntryPoint(const Info& info, EmitContext& ctx, Id main) {
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const std::span interfaces(ctx.interfaces.data(), ctx.interfaces.size());
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spv::ExecutionModel execution_model{};
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switch (info.l_stage) {
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case LogicalStage::Compute: {
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const std::array<u32, 3> workgroup_size{ctx.runtime_info.cs_info.workgroup_size};
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execution_model = spv::ExecutionModel::GLCompute;
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ctx.AddExecutionMode(main, spv::ExecutionMode::LocalSize, workgroup_size[0],
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workgroup_size[1], workgroup_size[2]);
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break;
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}
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case LogicalStage::Vertex:
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execution_model = spv::ExecutionModel::Vertex;
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break;
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case LogicalStage::TessellationControl:
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execution_model = spv::ExecutionModel::TessellationControl;
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ctx.AddCapability(spv::Capability::Tessellation);
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ctx.AddExecutionMode(main, spv::ExecutionMode::OutputVertices,
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ctx.runtime_info.hs_info.NumOutputControlPoints());
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break;
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case LogicalStage::TessellationEval: {
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execution_model = spv::ExecutionModel::TessellationEvaluation;
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const auto& vs_info = ctx.runtime_info.vs_info;
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ctx.AddExecutionMode(main, ExecutionMode(vs_info.tess_type));
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ctx.AddExecutionMode(main, ExecutionMode(vs_info.tess_partitioning));
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ctx.AddExecutionMode(main,
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vs_info.tess_topology == AmdGpu::TessellationTopology::TriangleCcw
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? spv::ExecutionMode::VertexOrderCcw
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: spv::ExecutionMode::VertexOrderCw);
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break;
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}
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case LogicalStage::Fragment:
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execution_model = spv::ExecutionModel::Fragment;
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if (ctx.profile.lower_left_origin_mode) {
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ctx.AddExecutionMode(main, spv::ExecutionMode::OriginLowerLeft);
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} else {
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ctx.AddExecutionMode(main, spv::ExecutionMode::OriginUpperLeft);
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}
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if (info.has_discard) {
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ctx.AddCapability(spv::Capability::DemoteToHelperInvocation);
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}
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if (info.stores.GetAny(IR::Attribute::Depth)) {
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ctx.AddExecutionMode(main, spv::ExecutionMode::DepthReplacing);
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}
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break;
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case LogicalStage::Geometry:
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execution_model = spv::ExecutionModel::Geometry;
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ctx.AddExecutionMode(main, GetInputPrimitiveType(ctx.runtime_info.gs_info.in_primitive));
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ctx.AddExecutionMode(main,
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GetOutputPrimitiveType(ctx.runtime_info.gs_info.out_primitive[0]));
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ctx.AddExecutionMode(main, spv::ExecutionMode::OutputVertices,
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ctx.runtime_info.gs_info.output_vertices);
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ctx.AddExecutionMode(main, spv::ExecutionMode::Invocations,
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ctx.runtime_info.gs_info.num_invocations);
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break;
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default:
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UNREACHABLE_MSG("Stage {}", u32(info.stage));
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}
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ctx.AddEntryPoint(execution_model, main, "main", interfaces);
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}
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void SetupFloatMode(EmitContext& ctx, const Profile& profile, const RuntimeInfo& runtime_info,
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Id main_func) {
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ctx.AddExtension("SPV_KHR_float_controls");
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const auto fp_denorm_mode = runtime_info.fp_denorm_mode32;
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if (fp_denorm_mode == AmdGpu::FpDenormMode::InOutFlush) {
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if (profile.support_fp32_denorm_flush) {
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ctx.AddCapability(spv::Capability::DenormFlushToZero);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::DenormFlushToZero, 32U);
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}
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} else {
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LOG_WARNING(Render_Vulkan, "Unknown FP denorm mode {}", u32(fp_denorm_mode));
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}
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const auto fp_round_mode = runtime_info.fp_round_mode32;
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if (fp_round_mode == AmdGpu::FpRoundMode::ToZero) {
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if (profile.support_fp32_round_to_zero) {
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ctx.AddCapability(spv::Capability::RoundingModeRTZ);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::RoundingModeRTZ, 32U);
|
|
}
|
|
} else if (fp_round_mode != AmdGpu::FpRoundMode::NearestEven) {
|
|
LOG_WARNING(Render_Vulkan, "Unknown FP rounding mode {}", u32(fp_round_mode));
|
|
}
|
|
}
|
|
|
|
void PatchPhiNodes(const IR::Program& program, EmitContext& ctx) {
|
|
auto inst{program.blocks.front()->begin()};
|
|
size_t block_index{0};
|
|
ctx.PatchDeferredPhi([&](u32 phi_arg, Id first_parent) {
|
|
if (phi_arg == 0) {
|
|
++inst;
|
|
if (inst == program.blocks[block_index]->end() ||
|
|
inst->GetOpcode() != IR::Opcode::Phi) {
|
|
do {
|
|
++block_index;
|
|
inst = program.blocks[block_index]->begin();
|
|
} while (inst->GetOpcode() != IR::Opcode::Phi);
|
|
}
|
|
}
|
|
const Id arg = ctx.Def(inst->Arg(phi_arg));
|
|
const Id parent = ctx.first_to_last_label_map[first_parent.value];
|
|
return std::make_pair(arg, parent);
|
|
});
|
|
}
|
|
} // Anonymous namespace
|
|
|
|
std::vector<u32> EmitSPIRV(const Profile& profile, const RuntimeInfo& runtime_info,
|
|
const IR::Program& program, Bindings& binding) {
|
|
EmitContext ctx{profile, runtime_info, program.info, binding};
|
|
const Id main{DefineMain(ctx, program)};
|
|
DefineEntryPoint(program.info, ctx, main);
|
|
SetupCapabilities(program.info, profile, ctx);
|
|
SetupFloatMode(ctx, profile, runtime_info, main);
|
|
PatchPhiNodes(program, ctx);
|
|
binding.user_data += program.info.ud_mask.NumRegs();
|
|
return ctx.Assemble();
|
|
}
|
|
|
|
Id EmitPhi(EmitContext& ctx, IR::Inst* inst) {
|
|
const size_t num_args{inst->NumArgs()};
|
|
boost::container::small_vector<Id, 32> blocks;
|
|
blocks.reserve(num_args);
|
|
for (size_t index = 0; index < num_args; ++index) {
|
|
blocks.push_back(inst->PhiBlock(index)->Definition<Id>());
|
|
}
|
|
// The type of a phi instruction is stored in its flags
|
|
const Id result_type{TypeId(ctx, inst->Flags<IR::Type>())};
|
|
return ctx.DeferredOpPhi(result_type, std::span(blocks.data(), blocks.size()));
|
|
}
|
|
|
|
void EmitVoid(EmitContext&) {}
|
|
|
|
Id EmitIdentity(EmitContext& ctx, const IR::Value& value) {
|
|
throw NotImplementedException("Forward identity declaration");
|
|
}
|
|
|
|
Id EmitConditionRef(EmitContext& ctx, const IR::Value& value) {
|
|
const Id id{ctx.Def(value)};
|
|
if (!Sirit::ValidId(id)) {
|
|
throw NotImplementedException("Forward identity declaration");
|
|
}
|
|
return id;
|
|
}
|
|
|
|
void EmitReference(EmitContext&) {}
|
|
|
|
void EmitPhiMove(EmitContext&) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitGetScc(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitGetExec(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitGetVcc(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitGetSccLo(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitGetVccLo(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitGetVccHi(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitGetM0(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitSetScc(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitSetExec(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitSetVcc(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitSetSccLo(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitSetVccLo(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitSetVccHi(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
void EmitSetM0(EmitContext& ctx) {
|
|
UNREACHABLE_MSG("Unreachable instruction");
|
|
}
|
|
|
|
} // namespace Shader::Backend::SPIRV
|