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ca92e72efe
* shader_recompiler: Various fixes to shared memory and atomics. * shader_recompiler: Re-type non-32bit load/stores.
90 lines
3.6 KiB
C++
90 lines
3.6 KiB
C++
// SPDX-FileCopyrightText: Copyright 2025 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include "shader_recompiler/backend/spirv/spirv_emit_context.h"
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namespace Shader::Backend::SPIRV {
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template <u32 bit_size, u32 num_components = 1, bool is_float = false>
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std::tuple<Id, Id> ResolveTypeAndZero(EmitContext& ctx) {
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Id result_type{};
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Id zero_value{};
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if constexpr (bit_size == 64 && num_components == 1 && !is_float) {
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result_type = ctx.U64;
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zero_value = ctx.u64_zero_value;
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} else if constexpr (bit_size == 32) {
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if (is_float) {
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result_type = ctx.F32[num_components];
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zero_value = ctx.f32_zero_value;
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} else {
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result_type = ctx.U32[num_components];
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zero_value = ctx.u32_zero_value;
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}
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} else if constexpr (bit_size == 16 && num_components == 1 && !is_float) {
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result_type = ctx.U16;
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zero_value = ctx.u16_zero_value;
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} else if constexpr (bit_size == 8 && num_components == 1 && !is_float) {
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result_type = ctx.U8;
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zero_value = ctx.u8_zero_value;
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} else {
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static_assert(false, "Type not supported.");
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}
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if (num_components > 1) {
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std::array<Id, num_components> zero_ids;
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zero_ids.fill(zero_value);
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zero_value = ctx.ConstantComposite(result_type, zero_ids);
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}
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return {result_type, zero_value};
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}
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template <u32 bit_size, u32 num_components = 1, bool is_float = false>
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auto AccessBoundsCheck(EmitContext& ctx, Id index, Id buffer_size, auto emit_func) {
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if (Sirit::ValidId(buffer_size)) {
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// Bounds checking enabled, wrap in a conditional branch to make sure that
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// the atomic is not mistakenly executed when the index is out of bounds.
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auto compare_index = index;
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if (num_components > 1) {
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compare_index = ctx.OpIAdd(ctx.U32[1], index, ctx.ConstU32(num_components - 1));
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}
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const Id in_bounds = ctx.OpULessThan(ctx.U1[1], compare_index, buffer_size);
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const Id ib_label = ctx.OpLabel();
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const Id end_label = ctx.OpLabel();
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ctx.OpSelectionMerge(end_label, spv::SelectionControlMask::MaskNone);
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ctx.OpBranchConditional(in_bounds, ib_label, end_label);
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const auto last_label = ctx.last_label;
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ctx.AddLabel(ib_label);
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const auto ib_result = emit_func();
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ctx.OpBranch(end_label);
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ctx.AddLabel(end_label);
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if (Sirit::ValidId(ib_result)) {
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const auto [result_type, zero_value] =
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ResolveTypeAndZero<bit_size, num_components, is_float>(ctx);
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return ctx.OpPhi(result_type, ib_result, ib_label, zero_value, last_label);
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} else {
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return Id{0};
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}
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}
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// Bounds checking not enabled, just perform the atomic operation.
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return emit_func();
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}
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template <u32 bit_size, u32 num_components = 1, bool is_float = false>
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static Id LoadAccessBoundsCheck(EmitContext& ctx, Id index, Id buffer_size, Id result) {
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if (Sirit::ValidId(buffer_size)) {
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// Bounds checking enabled, wrap in a select.
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auto compare_index = index;
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if (num_components > 1) {
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compare_index = ctx.OpIAdd(ctx.U32[1], index, ctx.ConstU32(num_components - 1));
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}
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const Id in_bounds = ctx.OpULessThan(ctx.U1[1], compare_index, buffer_size);
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const auto [result_type, zero_value] =
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ResolveTypeAndZero<bit_size, num_components, is_float>(ctx);
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return ctx.OpSelect(result_type, in_bounds, result, zero_value);
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}
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// Bounds checking not enabled, just return the plain value.
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return result;
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}
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} // namespace Shader::Backend::SPIRV
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