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https://github.com/shadps4-emu/shadPS4.git
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6ceab6dfac
* shader_recompiler: Add LDEXP * shader_recompiler: Add most image integer atomic ops * shader_recompiler: Implement shared memory load/store * shader_recompiler: More image atomics * externals: Update sirit * clang format * cmake: Add missing files * shader_recompiler: Fix some atomic bugs * shader_recompiler: Vs outputs * shader_recompiler: Shared mem has side-effects, fix format component order * shader_recompiler: Inline constant buffer impl * video_core: Fix regressions * Work * Fixup a few things
52 lines
1.8 KiB
C++
52 lines
1.8 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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namespace Shader::Gcn {
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static constexpr u32 SQ_SRC_LITERAL = 0xFF;
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void Translator::S_LOAD_DWORD(int num_dwords, const GcnInst& inst) {
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const auto& smrd = inst.control.smrd;
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const u32 dword_offset = [&] -> u32 {
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if (smrd.imm) {
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return smrd.offset;
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}
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if (smrd.offset == SQ_SRC_LITERAL) {
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return inst.src[1].code;
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}
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UNREACHABLE();
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}();
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const IR::ScalarReg sbase{inst.src[0].code * 2};
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const IR::Value base =
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ir.CompositeConstruct(ir.GetScalarReg(sbase), ir.GetScalarReg(sbase + 1));
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IR::ScalarReg dst_reg{inst.dst[0].code};
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for (u32 i = 0; i < num_dwords; i++) {
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ir.SetScalarReg(dst_reg++, ir.ReadConst(base, ir.Imm32(dword_offset + i)));
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}
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}
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void Translator::S_BUFFER_LOAD_DWORD(int num_dwords, const GcnInst& inst) {
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const auto& smrd = inst.control.smrd;
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const IR::ScalarReg sbase{inst.src[0].code * 2};
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const IR::U32 dword_offset = [&] -> IR::U32 {
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if (smrd.imm) {
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return ir.Imm32(smrd.offset);
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}
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if (smrd.offset == SQ_SRC_LITERAL) {
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return ir.Imm32(inst.src[1].code);
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}
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return ir.ShiftRightLogical(ir.GetScalarReg(IR::ScalarReg(smrd.offset)), ir.Imm32(2));
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}();
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const IR::Value vsharp =
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ir.CompositeConstruct(ir.GetScalarReg(sbase), ir.GetScalarReg(sbase + 1),
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ir.GetScalarReg(sbase + 2), ir.GetScalarReg(sbase + 3));
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IR::ScalarReg dst_reg{inst.dst[0].code};
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for (u32 i = 0; i < num_dwords; i++) {
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const IR::U32 index = ir.IAdd(dword_offset, ir.Imm32(i));
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ir.SetScalarReg(dst_reg++, ir.ReadConstBuffer(vsharp, index));
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}
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}
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} // namespace Shader::Gcn
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