mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-14 08:12:16 +00:00
509 lines
17 KiB
C++
509 lines
17 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "common/config.h"
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#include "common/io_file.h"
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#include "common/path_util.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/fetch_shader.h"
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/info.h"
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#include "shader_recompiler/runtime_info.h"
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#include "video_core/amdgpu/resource.h"
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#define MAGIC_ENUM_RANGE_MIN 0
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#define MAGIC_ENUM_RANGE_MAX 1515
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#include "magic_enum.hpp"
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namespace Shader::Gcn {
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Translator::Translator(IR::Block* block_, Info& info_, const RuntimeInfo& runtime_info_,
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const Profile& profile_)
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: ir{*block_, block_->begin()}, info{info_}, runtime_info{runtime_info_}, profile{profile_} {}
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void Translator::EmitPrologue() {
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ir.Prologue();
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ir.SetExec(ir.Imm1(true));
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// Initialize user data.
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IR::ScalarReg dst_sreg = IR::ScalarReg::S0;
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for (u32 i = 0; i < runtime_info.num_user_data; i++) {
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ir.SetScalarReg(dst_sreg, ir.GetUserData(dst_sreg));
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++dst_sreg;
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}
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IR::VectorReg dst_vreg = IR::VectorReg::V0;
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switch (info.stage) {
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case Stage::Vertex:
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// v0: vertex ID, always present
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::VertexId));
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// v1: instance ID, step rate 0
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if (runtime_info.num_input_vgprs > 0) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId0));
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}
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// v2: instance ID, step rate 1
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if (runtime_info.num_input_vgprs > 1) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId1));
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}
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// v3: instance ID, plain
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if (runtime_info.num_input_vgprs > 2) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId));
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}
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break;
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case Stage::Fragment:
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// https://github.com/chaotic-cx/mesa-mirror/blob/72326e15/src/amd/vulkan/radv_shader_args.c#L258
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// The first two VGPRs are used for i/j barycentric coordinates. In the vast majority of
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// cases it will be only those two, but if shader is using both e.g linear and perspective
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// inputs it can be more For now assume that this isn't the case.
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dst_vreg = IR::VectorReg::V2;
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for (u32 i = 0; i < 4; i++) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttribute(IR::Attribute::FragCoord, i));
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}
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::IsFrontFace));
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break;
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case Stage::Compute:
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 0));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 1));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 2));
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if (runtime_info.cs_info.tgid_enable[0]) {
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 0));
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}
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if (runtime_info.cs_info.tgid_enable[1]) {
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 1));
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}
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if (runtime_info.cs_info.tgid_enable[2]) {
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 2));
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}
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break;
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default:
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throw NotImplementedException("Unknown shader stage");
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}
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}
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template <typename T>
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T Translator::GetSrc(const InstOperand& operand) {
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constexpr bool is_float = std::is_same_v<T, IR::F32>;
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const auto get_imm = [&](auto value) -> T {
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if constexpr (is_float) {
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return ir.Imm32(std::bit_cast<float>(value));
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} else {
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return ir.Imm32(std::bit_cast<u32>(value));
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}
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};
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T value{};
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switch (operand.field) {
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case OperandField::ScalarGPR:
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value = ir.GetScalarReg<T>(IR::ScalarReg(operand.code));
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break;
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case OperandField::VectorGPR:
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value = ir.GetVectorReg<T>(IR::VectorReg(operand.code));
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break;
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case OperandField::ConstZero:
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value = get_imm(0U);
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break;
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case OperandField::SignedConstIntPos:
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value = get_imm(operand.code - SignedConstIntPosMin + 1);
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break;
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case OperandField::SignedConstIntNeg:
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value = get_imm(-s32(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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value = get_imm(operand.code);
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break;
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case OperandField::ConstFloatPos_1_0:
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value = get_imm(1.f);
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break;
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case OperandField::ConstFloatPos_0_5:
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value = get_imm(0.5f);
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break;
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case OperandField::ConstFloatPos_2_0:
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value = get_imm(2.0f);
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break;
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case OperandField::ConstFloatPos_4_0:
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value = get_imm(4.0f);
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break;
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case OperandField::ConstFloatNeg_0_5:
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value = get_imm(-0.5f);
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break;
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case OperandField::ConstFloatNeg_1_0:
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value = get_imm(-1.0f);
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break;
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case OperandField::ConstFloatNeg_2_0:
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value = get_imm(-2.0f);
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break;
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case OperandField::ConstFloatNeg_4_0:
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value = get_imm(-4.0f);
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break;
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case OperandField::VccLo:
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if constexpr (is_float) {
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value = ir.BitCast<IR::F32>(ir.GetVccLo());
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} else {
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value = ir.GetVccLo();
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}
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break;
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case OperandField::VccHi:
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if constexpr (is_float) {
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value = ir.BitCast<IR::F32>(ir.GetVccHi());
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} else {
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value = ir.GetVccHi();
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}
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break;
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case OperandField::M0:
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if constexpr (is_float) {
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value = ir.BitCast<IR::F32>(ir.GetM0());
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} else {
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value = ir.GetM0();
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}
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break;
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default:
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UNREACHABLE();
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}
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if constexpr (is_float) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(value);
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}
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(value);
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}
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} else {
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if (operand.input_modifier.abs) {
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value = ir.IAbs(value);
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}
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if (operand.input_modifier.neg) {
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UNREACHABLE();
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}
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}
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return value;
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}
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template IR::U32 Translator::GetSrc<IR::U32>(const InstOperand&);
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template IR::F32 Translator::GetSrc<IR::F32>(const InstOperand&);
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template <typename T>
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T Translator::GetSrc64(const InstOperand& operand) {
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constexpr bool is_float = std::is_same_v<T, IR::F64>;
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const auto get_imm = [&](auto value) -> T {
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if constexpr (is_float) {
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return ir.Imm64(std::bit_cast<double>(value));
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} else {
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return ir.Imm64(std::bit_cast<u64>(value));
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}
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};
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T value{};
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switch (operand.field) {
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case OperandField::ScalarGPR: {
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const auto value_lo = ir.GetScalarReg(IR::ScalarReg(operand.code));
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const auto value_hi = ir.GetScalarReg(IR::ScalarReg(operand.code + 1));
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if constexpr (is_float) {
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UNREACHABLE();
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} else {
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value = ir.PackUint2x32(ir.CompositeConstruct(value_lo, value_hi));
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}
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break;
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}
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case OperandField::VectorGPR: {
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const auto value_lo = ir.GetVectorReg(IR::VectorReg(operand.code));
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const auto value_hi = ir.GetVectorReg(IR::VectorReg(operand.code + 1));
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if constexpr (is_float) {
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value = ir.PackFloat2x32(ir.CompositeConstruct(value_lo, value_hi));
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} else {
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value = ir.PackUint2x32(ir.CompositeConstruct(value_lo, value_hi));
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}
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break;
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}
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case OperandField::ConstZero:
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value = get_imm(0ULL);
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break;
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case OperandField::SignedConstIntPos:
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value = get_imm(s64(operand.code) - SignedConstIntPosMin + 1);
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break;
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case OperandField::SignedConstIntNeg:
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value = get_imm(-s64(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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value = get_imm(u64(operand.code));
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break;
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case OperandField::ConstFloatPos_1_0:
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value = get_imm(1.0);
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break;
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case OperandField::ConstFloatPos_0_5:
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value = get_imm(0.5);
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break;
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case OperandField::ConstFloatPos_2_0:
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value = get_imm(2.0);
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break;
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case OperandField::ConstFloatPos_4_0:
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value = get_imm(4.0);
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break;
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case OperandField::ConstFloatNeg_0_5:
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value = get_imm(-0.5);
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break;
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case OperandField::ConstFloatNeg_1_0:
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value = get_imm(-1.0);
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break;
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case OperandField::ConstFloatNeg_2_0:
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value = get_imm(-2.0);
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break;
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case OperandField::ConstFloatNeg_4_0:
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value = get_imm(-4.0);
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break;
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case OperandField::VccLo:
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if constexpr (is_float) {
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UNREACHABLE();
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} else {
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value = ir.PackUint2x32(ir.CompositeConstruct(ir.GetVccLo(), ir.GetVccHi()));
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}
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break;
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case OperandField::VccHi:
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default:
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UNREACHABLE();
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}
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if constexpr (is_float) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(value);
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}
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(value);
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}
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}
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return value;
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}
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template IR::U64 Translator::GetSrc64<IR::U64>(const InstOperand&);
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template IR::F64 Translator::GetSrc64<IR::F64>(const InstOperand&);
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void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
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IR::U32F32 result = value;
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if (value.Type() == IR::Type::F32) {
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if (operand.output_modifier.multiplier != 0.f) {
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result = ir.FPMul(result, ir.Imm32(operand.output_modifier.multiplier));
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}
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if (operand.output_modifier.clamp) {
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result = ir.FPSaturate(value);
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}
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}
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switch (operand.field) {
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case OperandField::ScalarGPR:
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return ir.SetScalarReg(IR::ScalarReg(operand.code), result);
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case OperandField::VectorGPR:
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return ir.SetVectorReg(IR::VectorReg(operand.code), result);
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case OperandField::VccLo:
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return ir.SetVccLo(result);
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case OperandField::VccHi:
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return ir.SetVccHi(result);
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case OperandField::M0:
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return ir.SetM0(result);
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default:
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UNREACHABLE();
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}
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}
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void Translator::SetDst64(const InstOperand& operand, const IR::U64F64& value_raw) {
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IR::U64F64 value_untyped = value_raw;
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const bool is_float = value_raw.Type() == IR::Type::F64 || value_raw.Type() == IR::Type::F32;
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if (is_float) {
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if (operand.output_modifier.multiplier != 0.f) {
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value_untyped =
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ir.FPMul(value_untyped, ir.Imm64(f64(operand.output_modifier.multiplier)));
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}
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if (operand.output_modifier.clamp) {
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value_untyped = ir.FPSaturate(value_raw);
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}
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}
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const IR::U64 value =
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is_float ? ir.BitCast<IR::U64>(IR::F64{value_untyped}) : IR::U64{value_untyped};
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const IR::Value unpacked{ir.UnpackUint2x32(value)};
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const IR::U32 lo{ir.CompositeExtract(unpacked, 0U)};
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const IR::U32 hi{ir.CompositeExtract(unpacked, 1U)};
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switch (operand.field) {
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case OperandField::ScalarGPR:
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ir.SetScalarReg(IR::ScalarReg(operand.code + 1), hi);
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return ir.SetScalarReg(IR::ScalarReg(operand.code), lo);
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case OperandField::VectorGPR:
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ir.SetVectorReg(IR::VectorReg(operand.code + 1), hi);
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return ir.SetVectorReg(IR::VectorReg(operand.code), lo);
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case OperandField::VccLo:
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UNREACHABLE();
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case OperandField::VccHi:
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UNREACHABLE();
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case OperandField::M0:
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break;
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default:
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UNREACHABLE();
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}
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}
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void Translator::EmitFetch(const GcnInst& inst) {
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// Read the pointer to the fetch shader assembly.
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const u32 sgpr_base = inst.src[0].code;
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const u32* code;
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std::memcpy(&code, &info.user_data[sgpr_base], sizeof(code));
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// Parse the assembly to generate a list of attributes.
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u32 fetch_size{};
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const auto fetch_data = ParseFetchShader(code, &fetch_size);
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if (Config::dumpShaders()) {
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using namespace Common::FS;
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const auto dump_dir = GetUserPath(PathType::ShaderDir) / "dumps";
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if (!std::filesystem::exists(dump_dir)) {
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std::filesystem::create_directories(dump_dir);
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}
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const auto filename = fmt::format("vs_{:#018x}_fetch.bin", info.pgm_hash);
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const auto file = IOFile{dump_dir / filename, FileAccessMode::Write};
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file.WriteRaw<u8>(code, fetch_size);
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}
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info.vertex_offset_sgpr = fetch_data.vertex_offset_sgpr;
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info.instance_offset_sgpr = fetch_data.instance_offset_sgpr;
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for (const auto& attrib : fetch_data.attributes) {
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const IR::Attribute attr{IR::Attribute::Param0 + attrib.semantic};
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IR::VectorReg dst_reg{attrib.dest_vgpr};
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// Read the V# of the attribute to figure out component number and type.
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const auto buffer = info.ReadUd<AmdGpu::Buffer>(attrib.sgpr_base, attrib.dword_offset);
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for (u32 i = 0; i < 4; i++) {
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const IR::F32 comp = [&] {
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switch (buffer.GetSwizzle(i)) {
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case AmdGpu::CompSwizzle::One:
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return ir.Imm32(1.f);
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case AmdGpu::CompSwizzle::Zero:
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return ir.Imm32(0.f);
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case AmdGpu::CompSwizzle::Red:
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return ir.GetAttribute(attr, 0);
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case AmdGpu::CompSwizzle::Green:
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return ir.GetAttribute(attr, 1);
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case AmdGpu::CompSwizzle::Blue:
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return ir.GetAttribute(attr, 2);
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case AmdGpu::CompSwizzle::Alpha:
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return ir.GetAttribute(attr, 3);
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default:
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UNREACHABLE();
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}
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}();
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ir.SetVectorReg(dst_reg++, comp);
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}
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// In case of programmable step rates we need to fallback to instance data pulling in
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// shader, so VBs should be bound as regular data buffers
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s32 instance_buf_handle = -1;
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const auto step_rate = static_cast<Info::VsInput::InstanceIdType>(attrib.instance_data);
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if (step_rate == Info::VsInput::OverStepRate0 ||
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step_rate == Info::VsInput::OverStepRate1) {
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info.buffers.push_back({
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.sgpr_base = attrib.sgpr_base,
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.dword_offset = attrib.dword_offset,
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.used_types = IR::Type::F32,
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.is_instance_data = true,
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});
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instance_buf_handle = s32(info.buffers.size() - 1);
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info.uses_step_rates = true;
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}
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const u32 num_components = AmdGpu::NumComponents(buffer.GetDataFmt());
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info.vs_inputs.push_back({
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.fmt = buffer.GetNumberFmt(),
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.binding = attrib.semantic,
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.num_components = std::min<u16>(attrib.num_elements, num_components),
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.sgpr_base = attrib.sgpr_base,
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.dword_offset = attrib.dword_offset,
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.instance_step_rate = step_rate,
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.instance_data_buf = instance_buf_handle,
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});
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}
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}
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void Translator::EmitFlowControl(u32 pc, const GcnInst& inst) {
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switch (inst.opcode) {
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case Opcode::S_BARRIER:
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return S_BARRIER();
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case Opcode::S_TTRACEDATA:
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LOG_WARNING(Render_Vulkan, "S_TTRACEDATA instruction!");
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return;
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case Opcode::S_GETPC_B64:
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return S_GETPC_B64(pc, inst);
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case Opcode::S_WAITCNT:
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case Opcode::S_NOP:
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case Opcode::S_ENDPGM:
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case Opcode::S_CBRANCH_EXECZ:
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case Opcode::S_CBRANCH_SCC0:
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case Opcode::S_CBRANCH_SCC1:
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case Opcode::S_CBRANCH_VCCNZ:
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case Opcode::S_CBRANCH_VCCZ:
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case Opcode::S_CBRANCH_EXECNZ:
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case Opcode::S_BRANCH:
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return;
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default:
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UNREACHABLE();
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}
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}
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void Translator::LogMissingOpcode(const GcnInst& inst) {
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LOG_ERROR(Render_Recompiler, "Unknown opcode {} ({}, category = {})",
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magic_enum::enum_name(inst.opcode), u32(inst.opcode),
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magic_enum::enum_name(inst.category));
|
|
info.translation_failed = true;
|
|
}
|
|
|
|
void Translate(IR::Block* block, u32 pc, std::span<const GcnInst> inst_list, Info& info,
|
|
const RuntimeInfo& runtime_info, const Profile& profile) {
|
|
if (inst_list.empty()) {
|
|
return;
|
|
}
|
|
Translator translator{block, info, runtime_info, profile};
|
|
for (const auto& inst : inst_list) {
|
|
pc += inst.length;
|
|
|
|
// Special case for emitting fetch shader.
|
|
if (inst.opcode == Opcode::S_SWAPPC_B64) {
|
|
ASSERT(info.stage == Stage::Vertex);
|
|
translator.EmitFetch(inst);
|
|
continue;
|
|
}
|
|
|
|
// Emit instructions for each category.
|
|
switch (inst.category) {
|
|
case InstCategory::DataShare:
|
|
translator.EmitDataShare(inst);
|
|
break;
|
|
case InstCategory::VectorInterpolation:
|
|
translator.EmitVectorInterpolation(inst);
|
|
break;
|
|
case InstCategory::ScalarMemory:
|
|
translator.EmitScalarMemory(inst);
|
|
break;
|
|
case InstCategory::VectorMemory:
|
|
translator.EmitVectorMemory(inst);
|
|
break;
|
|
case InstCategory::Export:
|
|
translator.EmitExport(inst);
|
|
break;
|
|
case InstCategory::FlowControl:
|
|
translator.EmitFlowControl(pc, inst);
|
|
break;
|
|
case InstCategory::ScalarALU:
|
|
translator.EmitScalarAlu(inst);
|
|
break;
|
|
case InstCategory::VectorALU:
|
|
translator.EmitVectorAlu(inst);
|
|
break;
|
|
case InstCategory::DebugProfile:
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
}
|
|
}
|
|
|
|
} // namespace Shader::Gcn
|