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https://github.com/shadps4-emu/shadPS4.git
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a7c9bfa5c5
* translator: Implemtn f32 to f16 convert * shader_recompiler: Add bit instructions * shader_recompiler: More data share instructions * shader_recompiler: Remove exec contexts, fix S_MOV_B64 * shader_recompiler: Split instruction parsing into categories * shader_recompiler: Better BFS search * shader_recompiler: Constant propagation pass for cmp_class_f32 * shader_recompiler: Partial readfirstlane implementation * shader_recompiler: Stub readlane/writelane only for non-compute * hack: Fix swizzle on RDR * Will properly fix this when merging this * clang format * address_space: Bump user area size to full * shader_recompiler: V_INTERP_MOV_F32 * Should work the same as spirv will emit flat decoration on demand * kernel: Add MAP_OP_MAP_FLEXIBLE * image_view: Attempt to apply storage swizzle on format * vk_scheduler: Barrier attachments on renderpass end * clang format * liverpool: cs state backup * shader_recompiler: More instructions and formats * vector_alu: Proper V_MBCNT_U32_B32 * shader_recompiler: Port some dark souls things * file_system: Implement sceKernelRename * more formats * clang format * resource_tracking_pass: Back to assert * translate: Tracedata * kernel: Remove tracy lock * Solves random crashes in Dark Souls * code: Review comments
35 lines
1.2 KiB
C++
35 lines
1.2 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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namespace Shader::Gcn {
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void Translator::V_INTERP_P2_F32(const GcnInst& inst) {
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const IR::VectorReg dst_reg{inst.dst[0].code};
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auto& attr = info.ps_inputs.at(inst.control.vintrp.attr);
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const IR::Attribute attrib{IR::Attribute::Param0 + attr.param_index};
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ir.SetVectorReg(dst_reg, ir.GetAttribute(attrib, inst.control.vintrp.chan));
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}
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void Translator::V_INTERP_MOV_F32(const GcnInst& inst) {
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const IR::VectorReg dst_reg{inst.dst[0].code};
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auto& attr = info.ps_inputs.at(inst.control.vintrp.attr);
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const IR::Attribute attrib{IR::Attribute::Param0 + attr.param_index};
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ir.SetVectorReg(dst_reg, ir.GetAttribute(attrib, inst.control.vintrp.chan));
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}
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void Translator::EmitVectorInterpolation(const GcnInst& inst) {
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switch (inst.opcode) {
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case Opcode::V_INTERP_P1_F32:
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return;
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case Opcode::V_INTERP_P2_F32:
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return V_INTERP_P2_F32(inst);
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case Opcode::V_INTERP_MOV_F32:
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return V_INTERP_MOV_F32(inst);
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default:
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LogMissingOpcode(inst);
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}
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}
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} // namespace Shader::Gcn
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