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https://github.com/shadps4-emu/shadPS4.git
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b0d7feb292
* video_core: Implement conversion for uncommon/unsupported number formats. * shader_recompiler: Reinterpret image sample output as well. * liverpool_to_vk: Remove mappings for remapped number formats. These were poorly supported by drivers anyway. * resource_tracking_pass: Fix image write swizzle mistake. * amdgpu: Add missing specialization and move format mapping data to types * reinterpret: Fix U/SToF input type.
81 lines
2.7 KiB
C++
81 lines
2.7 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/ir/reinterpret.h"
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#include "shader_recompiler/runtime_info.h"
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namespace Shader::Gcn {
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void Translator::EmitExport(const GcnInst& inst) {
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if (ir.block->has_multiple_predecessors && info.stage == Stage::Fragment) {
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ir.Discard(ir.LogicalNot(ir.GetExec()));
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}
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const auto& exp = inst.control.exp;
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const IR::Attribute attrib{exp.target};
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if (attrib == IR::Attribute::Depth && exp.en != 0 && exp.en != 1) {
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LOG_WARNING(Render_Vulkan, "Unsupported depth export");
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return;
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}
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const std::array vsrc = {
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IR::VectorReg(inst.src[0].code),
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IR::VectorReg(inst.src[1].code),
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IR::VectorReg(inst.src[2].code),
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IR::VectorReg(inst.src[3].code),
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};
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const auto set_attribute = [&](u32 comp, IR::F32 value) {
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if (!IR::IsMrt(attrib)) {
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ir.SetAttribute(attrib, value, comp);
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return;
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}
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const u32 index = u32(attrib) - u32(IR::Attribute::RenderTarget0);
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const auto col_buf = runtime_info.fs_info.color_buffers[index];
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const auto converted = IR::ApplyWriteNumberConversion(ir, value, col_buf.num_conversion);
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const auto [r, g, b, a] = col_buf.swizzle;
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const std::array swizzle_array = {r, g, b, a};
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const auto swizzled_comp = swizzle_array[comp];
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if (u32(swizzled_comp) < u32(AmdGpu::CompSwizzle::Red)) {
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ir.SetAttribute(attrib, converted, comp);
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return;
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}
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ir.SetAttribute(attrib, converted, u32(swizzled_comp) - u32(AmdGpu::CompSwizzle::Red));
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};
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const auto unpack = [&](u32 idx) {
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const IR::Value value = ir.UnpackHalf2x16(ir.GetVectorReg(vsrc[idx]));
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const IR::F32 r = IR::F32{ir.CompositeExtract(value, 0)};
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const IR::F32 g = IR::F32{ir.CompositeExtract(value, 1)};
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set_attribute(idx * 2, r);
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set_attribute(idx * 2 + 1, g);
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};
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// Components are float16 packed into a VGPR
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if (exp.compr) {
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// Export R, G
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if (exp.en & 1) {
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unpack(0);
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}
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// Export B, A
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if ((exp.en >> 2) & 1) {
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unpack(1);
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}
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} else {
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// Components are float32 into separate VGPRS
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u32 mask = exp.en;
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for (u32 i = 0; i < 4; i++, mask >>= 1) {
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if ((mask & 1) == 0) {
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continue;
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}
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const IR::F32 comp = ir.GetVectorReg<IR::F32>(vsrc[i]);
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set_attribute(i, comp);
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}
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}
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if (IR::IsMrt(attrib)) {
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info.mrt_mask |= 1u << u8(attrib);
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}
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}
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} // namespace Shader::Gcn
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