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https://github.com/shadps4-emu/shadPS4.git
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fd3d3c4158
* shader_recompiler: Implement AMD buffer bounds checking behavior. * shader_recompiler: Use SRT flatbuf for bounds check size. * shader_recompiler: Fix buffer atomic bounds check. * buffer_cache: Prevent false image-to-buffer sync. Lowering vertex fetch to formatted buffer surfaced an issue where a CPU modified range may be overwritten with stale GPU modified image data. * Address review comments.
294 lines
8.9 KiB
C++
294 lines
8.9 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include <span>
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#include <vector>
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#include <boost/container/small_vector.hpp>
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#include <boost/container/static_vector.hpp>
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#include "common/assert.h"
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#include "common/types.h"
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#include "shader_recompiler/backend/bindings.h"
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#include "shader_recompiler/frontend/copy_shader.h"
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#include "shader_recompiler/frontend/tessellation.h"
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#include "shader_recompiler/ir/attribute.h"
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#include "shader_recompiler/ir/passes/srt.h"
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#include "shader_recompiler/ir/reg.h"
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#include "shader_recompiler/ir/type.h"
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#include "shader_recompiler/params.h"
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#include "shader_recompiler/profile.h"
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#include "shader_recompiler/runtime_info.h"
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#include "video_core/amdgpu/resource.h"
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namespace Shader {
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static constexpr size_t NumUserDataRegs = 16;
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static constexpr size_t NumImages = 64;
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static constexpr size_t NumBuffers = 32;
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static constexpr size_t NumSamplers = 16;
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static constexpr size_t NumFMasks = 8;
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enum class TextureType : u32 {
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Color1D,
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ColorArray1D,
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Color2D,
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ColorArray2D,
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Color3D,
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ColorCube,
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Buffer,
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};
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constexpr u32 NUM_TEXTURE_TYPES = 7;
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enum class BufferType : u32 {
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Guest,
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ReadConstUbo,
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GdsBuffer,
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SharedMemory,
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};
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struct Info;
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struct BufferResource {
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u32 sharp_idx;
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IR::Type used_types;
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AmdGpu::Buffer inline_cbuf;
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BufferType buffer_type;
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u8 instance_attrib{};
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bool is_written{};
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bool is_formatted{};
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bool IsSpecial() const noexcept {
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return buffer_type != BufferType::Guest;
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}
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bool IsStorage(const AmdGpu::Buffer& buffer, const Profile& profile) const noexcept {
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return buffer.GetSize() > profile.max_ubo_size || is_written;
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}
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[[nodiscard]] constexpr AmdGpu::Buffer GetSharp(const Info& info) const noexcept;
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};
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using BufferResourceList = boost::container::small_vector<BufferResource, NumBuffers>;
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struct ImageResource {
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u32 sharp_idx;
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bool is_depth{};
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bool is_atomic{};
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bool is_array{};
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bool is_written{};
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[[nodiscard]] constexpr AmdGpu::Image GetSharp(const Info& info) const noexcept;
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};
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using ImageResourceList = boost::container::small_vector<ImageResource, NumImages>;
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struct SamplerResource {
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u32 sharp_idx;
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AmdGpu::Sampler inline_sampler{};
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u32 associated_image : 4;
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u32 disable_aniso : 1;
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constexpr AmdGpu::Sampler GetSharp(const Info& info) const noexcept;
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};
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using SamplerResourceList = boost::container::small_vector<SamplerResource, NumSamplers>;
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struct FMaskResource {
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u32 sharp_idx;
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constexpr AmdGpu::Image GetSharp(const Info& info) const noexcept;
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};
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using FMaskResourceList = boost::container::small_vector<FMaskResource, NumFMasks>;
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struct PushData {
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static constexpr u32 Step0Index = 0;
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static constexpr u32 Step1Index = 1;
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static constexpr u32 XOffsetIndex = 2;
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static constexpr u32 YOffsetIndex = 3;
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static constexpr u32 XScaleIndex = 4;
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static constexpr u32 YScaleIndex = 5;
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static constexpr u32 UdRegsIndex = 6;
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static constexpr u32 BufOffsetIndex = UdRegsIndex + NumUserDataRegs / 4;
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u32 step0;
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u32 step1;
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float xoffset;
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float yoffset;
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float xscale;
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float yscale;
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std::array<u32, NumUserDataRegs> ud_regs;
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std::array<u8, NumBuffers> buf_offsets;
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void AddOffset(u32 binding, u32 offset) {
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ASSERT(offset < 256 && binding < buf_offsets.size());
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buf_offsets[binding] = offset;
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}
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};
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static_assert(sizeof(PushData) <= 128,
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"PushData size is greater than minimum size guaranteed by Vulkan spec");
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/**
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* Contains general information generated by the shader recompiler for an input program.
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*/
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struct Info {
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struct AttributeFlags {
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bool Get(IR::Attribute attrib, u32 comp = 0) const {
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return flags[Index(attrib)] & (1 << comp);
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}
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bool GetAny(IR::Attribute attrib) const {
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return flags[Index(attrib)];
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}
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void Set(IR::Attribute attrib, u32 comp = 0) {
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flags[Index(attrib)] |= (1 << comp);
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}
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u32 NumComponents(IR::Attribute attrib) const {
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return 4;
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}
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static size_t Index(IR::Attribute attrib) {
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return static_cast<size_t>(attrib);
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}
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std::array<u8, IR::NumAttributes> flags;
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};
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AttributeFlags loads{};
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AttributeFlags stores{};
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struct UserDataMask {
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void Set(IR::ScalarReg reg) noexcept {
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mask |= 1 << static_cast<u32>(reg);
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}
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u32 Index(IR::ScalarReg reg) const noexcept {
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const u32 reg_mask = (1 << static_cast<u32>(reg)) - 1;
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return std::popcount(mask & reg_mask);
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}
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u32 NumRegs() const noexcept {
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return std::popcount(mask);
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}
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u32 mask;
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};
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UserDataMask ud_mask{};
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CopyShaderData gs_copy_data;
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u32 uses_patches{};
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BufferResourceList buffers;
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ImageResourceList images;
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SamplerResourceList samplers;
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FMaskResourceList fmasks;
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PersistentSrtInfo srt_info;
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std::vector<u32> flattened_ud_buf;
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IR::ScalarReg tess_consts_ptr_base = IR::ScalarReg::Max;
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s32 tess_consts_dword_offset = -1;
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std::span<const u32> user_data;
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Stage stage;
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LogicalStage l_stage;
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u64 pgm_hash{};
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VAddr pgm_base;
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bool has_storage_images{};
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bool has_discard{};
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bool has_image_gather{};
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bool has_image_query{};
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bool uses_lane_id{};
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bool uses_group_quad{};
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bool uses_group_ballot{};
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bool uses_shared{};
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bool uses_fp16{};
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bool uses_fp64{};
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bool uses_pack_10_11_11{};
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bool uses_unpack_10_11_11{};
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bool stores_tess_level_outer{};
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bool stores_tess_level_inner{};
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bool translation_failed{};
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bool has_readconst{};
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u8 mrt_mask{0u};
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bool has_fetch_shader{false};
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u32 fetch_shader_sgpr_base{0u};
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explicit Info(Stage stage_, LogicalStage l_stage_, ShaderParams params)
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: stage{stage_}, l_stage{l_stage_}, pgm_hash{params.hash}, pgm_base{params.Base()},
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user_data{params.user_data} {}
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template <typename T>
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inline T ReadUdSharp(u32 sharp_idx) const noexcept {
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return *reinterpret_cast<const T*>(&flattened_ud_buf[sharp_idx]);
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}
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template <typename T>
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T ReadUdReg(u32 ptr_index, u32 dword_offset) const noexcept {
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T data;
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const u32* base = user_data.data();
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if (ptr_index != IR::NumScalarRegs) {
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std::memcpy(&base, &user_data[ptr_index], sizeof(base));
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base = reinterpret_cast<const u32*>(VAddr(base) & 0xFFFFFFFFFFFFULL);
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}
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std::memcpy(&data, base + dword_offset, sizeof(T));
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return data;
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}
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void PushUd(Backend::Bindings& bnd, PushData& push) const {
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u32 mask = ud_mask.mask;
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while (mask) {
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const u32 index = std::countr_zero(mask);
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ASSERT(bnd.user_data < NumUserDataRegs && index < NumUserDataRegs);
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mask &= ~(1U << index);
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push.ud_regs[bnd.user_data++] = user_data[index];
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}
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}
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void AddBindings(Backend::Bindings& bnd) const {
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bnd.buffer += buffers.size();
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bnd.unified += buffers.size() + images.size() + samplers.size();
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bnd.user_data += ud_mask.NumRegs();
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}
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void RefreshFlatBuf() {
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flattened_ud_buf.resize(srt_info.flattened_bufsize_dw);
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ASSERT(user_data.size() <= NumUserDataRegs);
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std::memcpy(flattened_ud_buf.data(), user_data.data(), user_data.size_bytes());
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// Run the JIT program to walk the SRT and write the leaves to a flat buffer
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if (srt_info.walker_func) {
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srt_info.walker_func(user_data.data(), flattened_ud_buf.data());
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}
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}
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void ReadTessConstantBuffer(TessellationDataConstantBuffer& tess_constants) const {
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ASSERT(tess_consts_dword_offset >= 0); // We've already tracked the V# UD
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auto buf = ReadUdReg<AmdGpu::Buffer>(static_cast<u32>(tess_consts_ptr_base),
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static_cast<u32>(tess_consts_dword_offset));
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VAddr tess_constants_addr = buf.base_address;
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memcpy(&tess_constants,
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reinterpret_cast<TessellationDataConstantBuffer*>(tess_constants_addr),
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sizeof(tess_constants));
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}
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};
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constexpr AmdGpu::Buffer BufferResource::GetSharp(const Info& info) const noexcept {
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return inline_cbuf ? inline_cbuf : info.ReadUdSharp<AmdGpu::Buffer>(sharp_idx);
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}
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constexpr AmdGpu::Image ImageResource::GetSharp(const Info& info) const noexcept {
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const auto image = info.ReadUdSharp<AmdGpu::Image>(sharp_idx);
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if (!image.Valid()) {
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// Fall back to null image if unbound.
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return AmdGpu::Image::Null();
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}
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return image;
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}
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constexpr AmdGpu::Sampler SamplerResource::GetSharp(const Info& info) const noexcept {
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return inline_sampler ? inline_sampler : info.ReadUdSharp<AmdGpu::Sampler>(sharp_idx);
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}
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constexpr AmdGpu::Image FMaskResource::GetSharp(const Info& info) const noexcept {
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return info.ReadUdSharp<AmdGpu::Image>(sharp_idx);
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}
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} // namespace Shader
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