mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-14 08:12:16 +00:00
eb844b9b63
* shader_recompiler: Implement manual barycentric interpolation path * clang format * emit_spirv: Fix typo * emit_spirv: Simplify variable definition * spirv_emit: clang format
444 lines
16 KiB
C++
444 lines
16 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <span>
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#include <type_traits>
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#include <utility>
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#include <vector>
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#include "common/assert.h"
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#include "common/func_traits.h"
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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#include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
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#include "shader_recompiler/backend/spirv/spirv_emit_context.h"
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/ir/basic_block.h"
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#include "shader_recompiler/ir/program.h"
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#include "video_core/amdgpu/types.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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static constexpr spv::ExecutionMode GetInputPrimitiveType(AmdGpu::PrimitiveType type) {
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switch (type) {
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case AmdGpu::PrimitiveType::PointList:
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return spv::ExecutionMode::InputPoints;
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case AmdGpu::PrimitiveType::LineList:
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return spv::ExecutionMode::InputLines;
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case AmdGpu::PrimitiveType::TriangleList:
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case AmdGpu::PrimitiveType::TriangleStrip:
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return spv::ExecutionMode::Triangles;
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case AmdGpu::PrimitiveType::AdjTriangleList:
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return spv::ExecutionMode::InputTrianglesAdjacency;
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default:
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UNREACHABLE_MSG("Unknown input primitive type {}", u32(type));
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}
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}
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static constexpr spv::ExecutionMode GetOutputPrimitiveType(AmdGpu::GsOutputPrimitiveType type) {
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switch (type) {
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case AmdGpu::GsOutputPrimitiveType::PointList:
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return spv::ExecutionMode::OutputVertices;
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case AmdGpu::GsOutputPrimitiveType::LineStrip:
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return spv::ExecutionMode::OutputLineStrip;
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case AmdGpu::GsOutputPrimitiveType::TriangleStrip:
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return spv::ExecutionMode::OutputTriangleStrip;
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default:
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UNREACHABLE_MSG("Unknown output primitive type {}", u32(type));
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}
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}
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template <auto func, typename... Args>
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void SetDefinition(EmitContext& ctx, IR::Inst* inst, Args... args) {
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inst->SetDefinition<Id>(func(ctx, std::forward<Args>(args)...));
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}
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template <typename ArgType>
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ArgType Arg(EmitContext& ctx, const IR::Value& arg) {
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if constexpr (std::is_same_v<ArgType, Id>) {
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return ctx.Def(arg);
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} else if constexpr (std::is_same_v<ArgType, const IR::Value&>) {
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return arg;
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} else if constexpr (std::is_same_v<ArgType, u32>) {
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return arg.U32();
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} else if constexpr (std::is_same_v<ArgType, u64>) {
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return arg.U64();
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} else if constexpr (std::is_same_v<ArgType, bool>) {
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return arg.U1();
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} else if constexpr (std::is_same_v<ArgType, IR::Attribute>) {
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return arg.Attribute();
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} else if constexpr (std::is_same_v<ArgType, IR::ScalarReg>) {
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return arg.ScalarReg();
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} else if constexpr (std::is_same_v<ArgType, IR::VectorReg>) {
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return arg.VectorReg();
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} else if constexpr (std::is_same_v<ArgType, const char*>) {
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return arg.StringLiteral();
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}
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}
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template <auto func, bool is_first_arg_inst, size_t... I>
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void Invoke(EmitContext& ctx, IR::Inst* inst, std::index_sequence<I...>) {
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using Traits = Common::FuncTraits<decltype(func)>;
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if constexpr (std::is_same_v<typename Traits::ReturnType, Id>) {
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if constexpr (is_first_arg_inst) {
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SetDefinition<func>(
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ctx, inst, inst,
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Arg<typename Traits::template ArgType<I + 2>>(ctx, inst->Arg(I))...);
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} else {
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SetDefinition<func>(
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ctx, inst, Arg<typename Traits::template ArgType<I + 1>>(ctx, inst->Arg(I))...);
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}
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} else {
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if constexpr (is_first_arg_inst) {
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func(ctx, inst, Arg<typename Traits::template ArgType<I + 2>>(ctx, inst->Arg(I))...);
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} else {
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func(ctx, Arg<typename Traits::template ArgType<I + 1>>(ctx, inst->Arg(I))...);
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}
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}
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}
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template <auto func>
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void Invoke(EmitContext& ctx, IR::Inst* inst) {
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using Traits = Common::FuncTraits<decltype(func)>;
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static_assert(Traits::NUM_ARGS >= 1, "Insufficient arguments");
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if constexpr (Traits::NUM_ARGS == 1) {
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Invoke<func, false>(ctx, inst, std::make_index_sequence<0>{});
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} else {
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using FirstArgType = typename Traits::template ArgType<1>;
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static constexpr bool is_first_arg_inst = std::is_same_v<FirstArgType, IR::Inst*>;
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using Indices = std::make_index_sequence<Traits::NUM_ARGS - (is_first_arg_inst ? 2 : 1)>;
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Invoke<func, is_first_arg_inst>(ctx, inst, Indices{});
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}
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}
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void EmitInst(EmitContext& ctx, IR::Inst* inst) {
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switch (inst->GetOpcode()) {
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#define OPCODE(name, result_type, ...) \
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case IR::Opcode::name: \
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return Invoke<&Emit##name>(ctx, inst);
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#include "shader_recompiler/ir/opcodes.inc"
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#undef OPCODE
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}
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UNREACHABLE_MSG("Invalid opcode {}", inst->GetOpcode());
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}
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Id TypeId(const EmitContext& ctx, IR::Type type) {
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switch (type) {
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case IR::Type::U1:
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return ctx.U1[1];
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case IR::Type::U32:
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return ctx.U32[1];
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default:
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throw NotImplementedException("Phi node type {}", type);
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}
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}
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void Traverse(EmitContext& ctx, const IR::Program& program) {
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IR::Block* current_block{};
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for (const IR::AbstractSyntaxNode& node : program.syntax_list) {
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switch (node.type) {
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case IR::AbstractSyntaxNode::Type::Block: {
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const Id label{node.data.block->Definition<Id>()};
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if (current_block) {
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ctx.OpBranch(label);
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}
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current_block = node.data.block;
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ctx.AddLabel(label);
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for (IR::Inst& inst : node.data.block->Instructions()) {
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EmitInst(ctx, &inst);
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}
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break;
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}
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case IR::AbstractSyntaxNode::Type::If: {
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const Id if_label{node.data.if_node.body->Definition<Id>()};
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const Id endif_label{node.data.if_node.merge->Definition<Id>()};
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ctx.OpSelectionMerge(endif_label, spv::SelectionControlMask::MaskNone);
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ctx.OpBranchConditional(ctx.Def(node.data.if_node.cond), if_label, endif_label);
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break;
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}
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case IR::AbstractSyntaxNode::Type::Loop: {
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const Id body_label{node.data.loop.body->Definition<Id>()};
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const Id continue_label{node.data.loop.continue_block->Definition<Id>()};
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const Id endloop_label{node.data.loop.merge->Definition<Id>()};
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ctx.OpLoopMerge(endloop_label, continue_label, spv::LoopControlMask::MaskNone);
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ctx.OpBranch(body_label);
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break;
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}
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case IR::AbstractSyntaxNode::Type::Break: {
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const Id break_label{node.data.break_node.merge->Definition<Id>()};
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const Id skip_label{node.data.break_node.skip->Definition<Id>()};
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ctx.OpBranchConditional(ctx.Def(node.data.break_node.cond), break_label, skip_label);
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break;
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}
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case IR::AbstractSyntaxNode::Type::EndIf:
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if (current_block) {
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ctx.OpBranch(node.data.end_if.merge->Definition<Id>());
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}
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break;
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case IR::AbstractSyntaxNode::Type::Repeat: {
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Id cond{ctx.Def(node.data.repeat.cond)};
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const Id loop_header_label{node.data.repeat.loop_header->Definition<Id>()};
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const Id merge_label{node.data.repeat.merge->Definition<Id>()};
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ctx.OpBranchConditional(cond, loop_header_label, merge_label);
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break;
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}
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case IR::AbstractSyntaxNode::Type::Return:
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ctx.OpReturn();
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break;
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case IR::AbstractSyntaxNode::Type::Unreachable:
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ctx.OpUnreachable();
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break;
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}
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if (node.type != IR::AbstractSyntaxNode::Type::Block) {
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current_block = nullptr;
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}
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}
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}
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Id DefineMain(EmitContext& ctx, const IR::Program& program) {
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const Id void_function{ctx.TypeFunction(ctx.void_id)};
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const Id main{ctx.OpFunction(ctx.void_id, spv::FunctionControlMask::MaskNone, void_function)};
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for (IR::Block* const block : program.blocks) {
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block->SetDefinition(ctx.OpLabel());
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}
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Traverse(ctx, program);
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ctx.OpFunctionEnd();
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return main;
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}
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void SetupCapabilities(const Info& info, const Profile& profile, EmitContext& ctx) {
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ctx.AddCapability(spv::Capability::Image1D);
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ctx.AddCapability(spv::Capability::Sampled1D);
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ctx.AddCapability(spv::Capability::ImageQuery);
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if (info.uses_fp16) {
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ctx.AddCapability(spv::Capability::Float16);
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ctx.AddCapability(spv::Capability::Int16);
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}
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if (info.uses_fp64) {
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ctx.AddCapability(spv::Capability::Float64);
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}
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ctx.AddCapability(spv::Capability::Int64);
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if (info.has_storage_images || info.has_image_buffers) {
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ctx.AddCapability(spv::Capability::StorageImageExtendedFormats);
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ctx.AddCapability(spv::Capability::StorageImageReadWithoutFormat);
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ctx.AddCapability(spv::Capability::StorageImageWriteWithoutFormat);
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}
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if (info.has_texel_buffers) {
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ctx.AddCapability(spv::Capability::SampledBuffer);
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}
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if (info.has_image_buffers) {
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ctx.AddCapability(spv::Capability::ImageBuffer);
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}
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if (info.has_image_gather) {
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ctx.AddCapability(spv::Capability::ImageGatherExtended);
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}
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if (info.has_image_query) {
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ctx.AddCapability(spv::Capability::ImageQuery);
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}
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if (info.uses_lane_id) {
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ctx.AddCapability(spv::Capability::GroupNonUniform);
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}
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if (info.uses_group_quad) {
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ctx.AddCapability(spv::Capability::GroupNonUniformQuad);
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}
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if (info.uses_group_ballot) {
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ctx.AddCapability(spv::Capability::GroupNonUniformBallot);
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}
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if (info.stage == Stage::Export || info.stage == Stage::Vertex) {
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ctx.AddExtension("SPV_KHR_shader_draw_parameters");
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ctx.AddCapability(spv::Capability::DrawParameters);
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}
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if (info.stage == Stage::Geometry) {
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ctx.AddCapability(spv::Capability::Geometry);
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}
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if (info.stage == Stage::Fragment && profile.needs_manual_interpolation) {
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ctx.AddExtension("SPV_KHR_fragment_shader_barycentric");
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ctx.AddCapability(spv::Capability::FragmentBarycentricKHR);
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}
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}
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void DefineEntryPoint(const IR::Program& program, EmitContext& ctx, Id main) {
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const auto& info = program.info;
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const std::span interfaces(ctx.interfaces.data(), ctx.interfaces.size());
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spv::ExecutionModel execution_model{};
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switch (program.info.stage) {
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case Stage::Compute: {
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const std::array<u32, 3> workgroup_size{ctx.runtime_info.cs_info.workgroup_size};
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execution_model = spv::ExecutionModel::GLCompute;
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ctx.AddExecutionMode(main, spv::ExecutionMode::LocalSize, workgroup_size[0],
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workgroup_size[1], workgroup_size[2]);
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break;
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}
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case Stage::Export:
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case Stage::Vertex:
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execution_model = spv::ExecutionModel::Vertex;
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break;
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case Stage::Fragment:
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execution_model = spv::ExecutionModel::Fragment;
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if (ctx.profile.lower_left_origin_mode) {
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ctx.AddExecutionMode(main, spv::ExecutionMode::OriginLowerLeft);
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} else {
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ctx.AddExecutionMode(main, spv::ExecutionMode::OriginUpperLeft);
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}
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if (info.has_discard) {
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ctx.AddExtension("SPV_EXT_demote_to_helper_invocation");
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ctx.AddCapability(spv::Capability::DemoteToHelperInvocationEXT);
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}
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if (info.stores.Get(IR::Attribute::Depth)) {
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ctx.AddExecutionMode(main, spv::ExecutionMode::DepthReplacing);
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}
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break;
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case Stage::Geometry:
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execution_model = spv::ExecutionModel::Geometry;
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ctx.AddExecutionMode(main, GetInputPrimitiveType(ctx.runtime_info.gs_info.in_primitive));
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ctx.AddExecutionMode(main,
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GetOutputPrimitiveType(ctx.runtime_info.gs_info.out_primitive[0]));
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ctx.AddExecutionMode(main, spv::ExecutionMode::OutputVertices,
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ctx.runtime_info.gs_info.output_vertices);
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ctx.AddExecutionMode(main, spv::ExecutionMode::Invocations,
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ctx.runtime_info.gs_info.num_invocations);
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break;
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default:
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throw NotImplementedException("Stage {}", u32(program.info.stage));
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}
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ctx.AddEntryPoint(execution_model, main, "main", interfaces);
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}
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void SetupFloatMode(EmitContext& ctx, const Profile& profile, const RuntimeInfo& runtime_info,
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Id main_func) {
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ctx.AddExtension("SPV_KHR_float_controls");
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const auto fp_denorm_mode = runtime_info.fp_denorm_mode32;
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if (fp_denorm_mode == AmdGpu::FpDenormMode::InOutFlush) {
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if (profile.support_fp32_denorm_flush) {
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ctx.AddCapability(spv::Capability::DenormFlushToZero);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::DenormFlushToZero, 32U);
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}
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} else {
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LOG_WARNING(Render_Vulkan, "Unknown FP denorm mode {}", u32(fp_denorm_mode));
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}
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const auto fp_round_mode = runtime_info.fp_round_mode32;
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if (fp_round_mode != AmdGpu::FpRoundMode::NearestEven) {
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LOG_WARNING(Render_Vulkan, "Unknown FP rounding mode {}", u32(fp_round_mode));
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}
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}
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void PatchPhiNodes(const IR::Program& program, EmitContext& ctx) {
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auto inst{program.blocks.front()->begin()};
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size_t block_index{0};
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ctx.PatchDeferredPhi([&](size_t phi_arg) {
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if (phi_arg == 0) {
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++inst;
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if (inst == program.blocks[block_index]->end() ||
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inst->GetOpcode() != IR::Opcode::Phi) {
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do {
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++block_index;
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inst = program.blocks[block_index]->begin();
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} while (inst->GetOpcode() != IR::Opcode::Phi);
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}
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}
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return ctx.Def(inst->Arg(phi_arg));
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});
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}
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} // Anonymous namespace
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std::vector<u32> EmitSPIRV(const Profile& profile, const RuntimeInfo& runtime_info,
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const IR::Program& program, Bindings& binding) {
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EmitContext ctx{profile, runtime_info, program.info, binding};
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const Id main{DefineMain(ctx, program)};
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DefineEntryPoint(program, ctx, main);
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SetupCapabilities(program.info, profile, ctx);
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SetupFloatMode(ctx, profile, runtime_info, main);
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PatchPhiNodes(program, ctx);
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binding.user_data += program.info.ud_mask.NumRegs();
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return ctx.Assemble();
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}
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Id EmitPhi(EmitContext& ctx, IR::Inst* inst) {
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const size_t num_args{inst->NumArgs()};
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boost::container::small_vector<Id, 32> blocks;
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blocks.reserve(num_args);
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for (size_t index = 0; index < num_args; ++index) {
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blocks.push_back(inst->PhiBlock(index)->Definition<Id>());
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}
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// The type of a phi instruction is stored in its flags
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const Id result_type{TypeId(ctx, inst->Flags<IR::Type>())};
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return ctx.DeferredOpPhi(result_type, std::span(blocks.data(), blocks.size()));
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}
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void EmitVoid(EmitContext&) {}
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Id EmitIdentity(EmitContext& ctx, const IR::Value& value) {
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throw NotImplementedException("Forward identity declaration");
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}
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Id EmitConditionRef(EmitContext& ctx, const IR::Value& value) {
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const Id id{ctx.Def(value)};
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if (!Sirit::ValidId(id)) {
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throw NotImplementedException("Forward identity declaration");
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}
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return id;
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}
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void EmitReference(EmitContext&) {}
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void EmitPhiMove(EmitContext&) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitGetScc(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitGetExec(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitGetVcc(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitGetSccLo(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitGetVccLo(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitGetVccHi(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitGetM0(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitSetScc(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitSetExec(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitSetVcc(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitSetSccLo(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitSetVccLo(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitSetVccHi(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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void EmitSetM0(EmitContext& ctx) {
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UNREACHABLE_MSG("Unreachable instruction");
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}
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} // namespace Shader::Backend::SPIRV
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