Added LCD registers, and implementation for color filling in OGL code.
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parent
47010fea31
commit
041e99b613
11 changed files with 234 additions and 37 deletions
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@ -87,6 +87,7 @@ set(SRCS
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hle/svc.cpp
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hw/gpu.cpp
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hw/hw.cpp
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hw/lcd.cpp
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loader/elf.cpp
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loader/loader.cpp
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loader/ncch.cpp
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@ -196,6 +197,7 @@ set(HEADERS
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hle/svc.h
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hw/gpu.h
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hw/hw.h
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hw/lcd.h
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loader/elf.h
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loader/loader.h
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loader/ncch.h
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@ -11,12 +11,16 @@
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#include "gsp_gpu.h"
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#include "core/hw/hw.h"
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#include "core/hw/gpu.h"
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#include "core/hw/lcd.h"
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#include "video_core/gpu_debugger.h"
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// Main graphics debugger object - TODO: Here is probably not the best place for this
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GraphicsDebugger g_debugger;
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// Beginning address of HW regs
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const static u32 REGS_BEGIN = 0x1EB00000;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Namespace GSP_GPU
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@ -87,7 +91,7 @@ static void WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* data) {
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return;
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while (size_in_bytes > 0) {
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HW::Write<u32>(base_address + 0x1EB00000, *data);
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HW::Write<u32>(base_address + REGS_BEGIN, *data);
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size_in_bytes -= 4;
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++data;
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@ -130,7 +134,7 @@ static void WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, const u32*
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return;
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while (size_in_bytes > 0) {
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const u32 reg_address = base_address + 0x1EB00000;
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const u32 reg_address = base_address + REGS_BEGIN;
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u32 reg_value;
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HW::Read<u32>(reg_value, reg_address);
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@ -190,7 +194,7 @@ static void ReadHWRegs(Service::Interface* self) {
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u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
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while (size > 0) {
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HW::Read<u32>(*dst, reg_addr + 0x1EB00000);
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HW::Read<u32>(*dst, reg_addr + REGS_BEGIN);
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size -= 4;
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++dst;
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@ -439,24 +443,18 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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* Outputs:
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* 1: Result code
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*/
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void SetLcdForceBlack(Service::Interface* self) {
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// TODO: currently has no effect, as LCD reg writes have nowhere to go.
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static void SetLcdForceBlack(Service::Interface* self) {
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u32* cmd_buff = Kernel::GetCommandBuffer();
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bool enable_black = cmd_buff[1] != 0;
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u32 data = 0;
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LCD::Regs::ColorFill data = {0};
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if (enable_black) {
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// Sets bit 24 to 1, enabling the fill
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// Since data is already 0x00000000, there is no need to explicitly set
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// bits 0-23 to zero (black), or bit 24 to 0 (fill disabled).
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data |= (1 << 24);
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}
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// Since data is already zeroed, there is no need to explicitly set
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// the color to black (all zero).
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data.is_enabled = enable_black;
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u32 data_main = data;
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u32 data_sub = data;
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WriteHWRegs(0x202204, 4, &data_main); // Main LCD
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WriteHWRegs(0x202A04, 4, &data_sub); // Sub LCD
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LCD::Write(HW::VADDR_LCD + 4 * LCD_REG_INDEX(color_fill_top), data.raw); // Top LCD
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LCD::Write(HW::VADDR_LCD + 4 * LCD_REG_INDEX(color_fill_bottom), data.raw); // Bottom LCD
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cmd_buff[1] = RESULT_SUCCESS.raw;
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}
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@ -246,6 +246,8 @@ struct Regs {
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return content[index];
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}
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#undef ASSERT_MEMBER_SIZE
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private:
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/*
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* Most physical addresses which GPU registers refer to are 8-byte aligned.
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@ -6,17 +6,19 @@
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#include "core/hw/hw.h"
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#include "core/hw/gpu.h"
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#include "core/hw/lcd.h"
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namespace HW {
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template <typename T>
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inline void Read(T &var, const u32 addr) {
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switch (addr & 0xFFFFF000) {
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case VADDR_GPU:
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GPU::Read(var, addr);
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break;
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case VADDR_LCD:
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LCD::Write(var, addr);
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break;
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default:
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LOG_ERROR(HW_Memory, "unknown Read%lu @ 0x%08X", sizeof(var) * 8, addr);
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}
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@ -25,11 +27,12 @@ inline void Read(T &var, const u32 addr) {
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template <typename T>
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inline void Write(u32 addr, const T data) {
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switch (addr & 0xFFFFF000) {
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case VADDR_GPU:
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GPU::Write(addr, data);
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break;
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case VADDR_LCD:
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LCD::Write(addr, data);
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break;
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default:
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LOG_ERROR(HW_Memory, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, addr);
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}
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@ -54,6 +57,7 @@ void Update() {
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/// Initialize hardware
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void Init() {
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GPU::Init();
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LCD::Init();
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LOG_DEBUG(HW, "initialized OK");
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}
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@ -8,8 +8,8 @@
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namespace HW {
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enum {
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VADDR_IO = 0x1EC00000,
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/// Beginnings of IO register regions, in the user VA space.
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enum : u32 {
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VADDR_HASH = 0x1EC01000,
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VADDR_CSND = 0x1EC03000,
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VADDR_DSP = 0x1EC40000,
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@ -25,9 +25,7 @@ enum {
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VADDR_SPI_3 = 0x1EC60000,
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VADDR_I2C_3 = 0x1EC61000,
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VADDR_MIC = 0x1EC62000,
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VADDR_PXI = 0x1EC63000, // 0xFFFD2000
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//VADDR_NTRCARD
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VADDR_CDMA = 0xFFFDA000, // CoreLink DMA-330? Info
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VADDR_PXI = 0x1EC63000,
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VADDR_LCD = 0x1ED02000,
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VADDR_DSP_2 = 0x1ED03000,
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VADDR_HASH_2 = 0x1EE01000,
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66
src/core/hw/lcd.cpp
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66
src/core/hw/lcd.cpp
Normal file
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@ -0,0 +1,66 @@
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// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/common_types.h"
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#include "core/arm/arm_interface.h"
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#include "core/hle/hle.h"
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#include "core/hw/hw.h"
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#include "core/hw/lcd.h"
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namespace LCD {
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Regs g_regs;
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template <typename T>
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inline void Read(T &var, const u32 raw_addr) {
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u32 addr = raw_addr - HW::VADDR_LCD;
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u32 index = addr / 4;
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// Reads other than u32 are untested, so I'd rather have them abort than silently fail
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if (index >= 0x400 || !std::is_same<T, u32>::value) {
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LOG_ERROR(HW_LCD, "unknown Read%lu @ 0x%08X", sizeof(var) * 8, addr);
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return;
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}
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var = g_regs[index];
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}
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template <typename T>
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inline void Write(u32 addr, const T data) {
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addr -= HW::VADDR_LCD;
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u32 index = addr / 4;
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// Writes other than u32 are untested, so I'd rather have them abort than silently fail
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if (index >= 0x400 || !std::is_same<T, u32>::value) {
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LOG_ERROR(HW_LCD, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, addr);
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return;
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}
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g_regs[index] = static_cast<u32>(data);
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}
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// Explicitly instantiate template functions because we aren't defining this in the header:
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template void Read<u64>(u64 &var, const u32 addr);
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template void Read<u32>(u32 &var, const u32 addr);
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template void Read<u16>(u16 &var, const u32 addr);
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template void Read<u8>(u8 &var, const u32 addr);
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template void Write<u64>(u32 addr, const u64 data);
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template void Write<u32>(u32 addr, const u32 data);
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template void Write<u16>(u32 addr, const u16 data);
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template void Write<u8>(u32 addr, const u8 data);
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/// Initialize hardware
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void Init() {
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LOG_DEBUG(HW_LCD, "initialized OK");
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}
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/// Shutdown hardware
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void Shutdown() {
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LOG_DEBUG(HW_LCD, "shutdown OK");
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}
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} // namespace
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88
src/core/hw/lcd.h
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88
src/core/hw/lcd.h
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@ -0,0 +1,88 @@
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// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <cstddef>
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#include "common/common_types.h"
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#include "common/bit_field.h"
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#define LCD_REG_INDEX(field_name) (offsetof(LCD::Regs, field_name) / sizeof(u32))
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namespace LCD {
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struct Regs {
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union ColorFill {
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u32 raw;
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BitField<0, 8, u32> color_r;
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BitField<8, 8, u32> color_g;
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BitField<16, 8, u32> color_b;
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BitField<24, 1, u32> is_enabled;
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};
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INSERT_PADDING_WORDS(0x81);
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ColorFill color_fill_top;
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INSERT_PADDING_WORDS(0xE);
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u32 backlight_top;
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INSERT_PADDING_WORDS(0x1F0);
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ColorFill color_fill_bottom;
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INSERT_PADDING_WORDS(0xE);
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u32 backlight_bottom;
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INSERT_PADDING_WORDS(0x16F);
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static inline size_t NumIds() {
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return sizeof(Regs) / sizeof(u32);
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}
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u32& operator [] (int index) const {
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u32* content = (u32*)this;
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return content[index];
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}
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u32& operator [] (int index) {
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u32* content = (u32*)this;
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return content[index];
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}
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#undef ASSERT_MEMBER_SIZE
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};
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static_assert(std::is_standard_layout<Regs>::value, "Structure does not use standard layout");
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// TODO: MSVC does not support using offsetof() on non-static data members even though this
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// is technically allowed since C++11. This macro should be enabled once MSVC adds
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// support for that.
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#ifndef _MSC_VER
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(Regs, field_name) == position * 4, \
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"Field "#field_name" has invalid position")
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ASSERT_REG_POSITION(color_fill_top, 0x81);
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ASSERT_REG_POSITION(backlight_top, 0x90);
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ASSERT_REG_POSITION(color_fill_bottom, 0x281);
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ASSERT_REG_POSITION(backlight_bottom, 0x290);
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#undef ASSERT_REG_POSITION
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#endif // !defined(_MSC_VER)
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extern Regs g_regs;
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template <typename T>
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void Read(T &var, const u32 addr);
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template <typename T>
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void Write(u32 addr, const T data);
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/// Initialize hardware
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void Init();
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/// Shutdown hardware
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void Shutdown();
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} // namespace
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