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shader_recompiler,video_core: Cleanup some GCC and Clang errors

Browse source 
Mostly fixing unused *, implicit conversion, braced scalar init,
fpermissive, and some others.

Some Clang errors likely remain in video_core, and std::ranges is still
a pertinent issue in shader_recompiler

shader_recompiler: cmake: Force bracket depth to 1024 on Clang
Increases the maximum fold expression depth

thread_worker: Include condition_variable

Don't use list initializers in control flow

Co-authored-by: ReinUsesLisp <reinuseslisp@airmail.cc>
This commit is contained in:
lat9nq 2021-04-05 22:25:22 -04:00 • committed by ameerj
parent 5cd3d00167
commit 0bb85f6a75
66 changed files with 308 additions and 313 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/shader_recompiler/frontend/ir/attribute.cpp
View file

@ -17,7 +17,7 @@ u32 GenericAttributeIndex(Attribute attribute) {
if (!IsGeneric(attribute)) {
throw InvalidArgument("Attribute is not generic {}", attribute);
}
return (static_cast<int>(attribute) - static_cast<int>(Attribute::Generic0X)) / 4;
return (static_cast<u32>(attribute) - static_cast<u32>(Attribute::Generic0X)) / 4u;
}
std::string NameOf(Attribute attribute) {
@ -444,4 +444,4 @@ std::string NameOf(Attribute attribute) {
return fmt::format("<reserved attribute {}>", static_cast<int>(attribute));
}
} // namespace Shader::IR
} // namespace Shader::IR

2
src/shader_recompiler/frontend/ir/basic_block.cpp
View file

@ -155,7 +155,7 @@ std::string DumpBlock(const Block& block, const std::map<const Block*, size_t>&
ret += fmt::format(": begin={:04x} end={:04x}\n", block.LocationBegin(), block.LocationEnd());
for (const Inst& inst : block) {
const Opcode op{inst.Opcode()};
const Opcode op{inst.GetOpcode()};
ret += fmt::format("[{:016x}] ", reinterpret_cast<u64>(&inst));
if (TypeOf(op) != Type::Void) {
ret += fmt::format("%{:<5} = {}", InstIndex(inst_to_index, inst_index, &inst), op);

6
src/shader_recompiler/frontend/ir/condition.cpp
View file

@ -12,10 +12,10 @@ namespace Shader::IR {
std::string NameOf(Condition condition) {
std::string ret;
if (condition.FlowTest() != FlowTest::T) {
ret = fmt::to_string(condition.FlowTest());
if (condition.GetFlowTest() != FlowTest::T) {
ret = fmt::to_string(condition.GetFlowTest());
}
const auto [pred, negated]{condition.Pred()};
const auto [pred, negated]{condition.GetPred()};
if (!ret.empty()) {
ret += '&';
}

4
src/shader_recompiler/frontend/ir/condition.h
View file

@ -30,11 +30,11 @@ public:
auto operator<=>(const Condition&) const noexcept = default;
[[nodiscard]] IR::FlowTest FlowTest() const noexcept {
[[nodiscard]] IR::FlowTest GetFlowTest() const noexcept {
return static_cast<IR::FlowTest>(flow_test);
}
[[nodiscard]] std::pair<IR::Pred, bool> Pred() const noexcept {
[[nodiscard]] std::pair<IR::Pred, bool> GetPred() const noexcept {
return {static_cast<IR::Pred>(pred), pred_negated != 0};
}

4
src/shader_recompiler/frontend/ir/ir_emitter.cpp
View file

@ -290,8 +290,8 @@ static U1 GetFlowTest(IREmitter& ir, FlowTest flow_test) {
}
U1 IREmitter::Condition(IR::Condition cond) {
const FlowTest flow_test{cond.FlowTest()};
const auto [pred, is_negated]{cond.Pred()};
const FlowTest flow_test{cond.GetFlowTest()};
const auto [pred, is_negated]{cond.GetPred()};
return LogicalAnd(GetPred(pred, is_negated), GetFlowTest(*this, flow_test));
}

16
src/shader_recompiler/frontend/ir/microinstruction.cpp
View file

@ -12,7 +12,7 @@
namespace Shader::IR {
namespace {
void CheckPseudoInstruction(IR::Inst* inst, IR::Opcode opcode) {
if (inst && inst->Opcode() != opcode) {
if (inst && inst->GetOpcode() != opcode) {
throw LogicError("Invalid pseudo-instruction");
}
}
@ -25,11 +25,17 @@ void SetPseudoInstruction(IR::Inst*& dest_inst, IR::Inst* pseudo_inst) {
}
void RemovePseudoInstruction(IR::Inst*& inst, IR::Opcode expected_opcode) {
if (inst->Opcode() != expected_opcode) {
if (inst->GetOpcode() != expected_opcode) {
throw LogicError("Undoing use of invalid pseudo-op");
}
inst = nullptr;
}
void AllocAssociatedInsts(std::unique_ptr<AssociatedInsts>& associated_insts) {
if (!associated_insts) {
associated_insts = std::make_unique<AssociatedInsts>();
}
}
} // Anonymous namespace
Inst::Inst(IR::Opcode op_, u32 flags_) noexcept : op{op_}, flags{flags_} {
@ -249,12 +255,6 @@ void Inst::ReplaceOpcode(IR::Opcode opcode) {
op = opcode;
}
void AllocAssociatedInsts(std::unique_ptr<AssociatedInsts>& associated_insts) {
if (!associated_insts) {
associated_insts = std::make_unique<AssociatedInsts>();
}
}
void Inst::Use(const Value& value) {
Inst* const inst{value.Inst()};
++inst->use_count;

4
src/shader_recompiler/frontend/ir/microinstruction.h
View file

@ -46,7 +46,7 @@ public:
}
/// Get the opcode this microinstruction represents.
[[nodiscard]] IR::Opcode Opcode() const noexcept {
[[nodiscard]] IR::Opcode GetOpcode() const noexcept {
return op;
}
@ -95,7 +95,7 @@ public:
requires(sizeof(FlagsType) <= sizeof(u32) && std::is_trivially_copyable_v<FlagsType>)
[[nodiscard]] FlagsType Flags() const noexcept {
FlagsType ret;
std::memcpy(&ret, &flags, sizeof(ret));
std::memcpy(reinterpret_cast<char*>(&ret), &flags, sizeof(ret));
return ret;
}

2
src/shader_recompiler/frontend/ir/opcodes.cpp
View file

@ -49,7 +49,7 @@ constexpr std::array META_TABLE{
#define OPCODE(name_token, type_token, ...) \
OpcodeMeta{ \
.name{#name_token}, \
.type{type_token}, \
.type = type_token, \
.arg_types{__VA_ARGS__}, \
},
#include "opcodes.inc"

2
src/shader_recompiler/frontend/ir/program.cpp
View file

@ -2,8 +2,6 @@
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#pragma once
#include <map>
#include <string>

4
src/shader_recompiler/frontend/ir/value.cpp
View file

@ -33,11 +33,11 @@ Value::Value(u64 value) noexcept : type{Type::U64}, imm_u64{value} {}
Value::Value(f64 value) noexcept : type{Type::F64}, imm_f64{value} {}
bool Value::IsIdentity() const noexcept {
return type == Type::Opaque && inst->Opcode() == Opcode::Identity;
return type == Type::Opaque && inst->GetOpcode() == Opcode::Identity;
}
bool Value::IsPhi() const noexcept {
return type == Type::Opaque && inst->Opcode() == Opcode::Phi;
return type == Type::Opaque && inst->GetOpcode() == Opcode::Phi;
}
bool Value::IsEmpty() const noexcept {

2
src/shader_recompiler/frontend/ir/value.h
View file

@ -94,7 +94,7 @@ public:
}
}
explicit TypedValue(IR::Inst* inst) : TypedValue(Value(inst)) {}
explicit TypedValue(IR::Inst* inst_) : TypedValue(Value(inst_)) {}
};
using U1 = TypedValue<Type::U1>;

140
src/shader_recompiler/frontend/maxwell/control_flow.cpp
View file

@ -34,41 +34,37 @@ struct Compare {
};
u32 BranchOffset(Location pc, Instruction inst) {
return pc.Offset() + inst.branch.Offset() + 8;
return pc.Offset() + static_cast<u32>(inst.branch.Offset()) + 8u;
}
void Split(Block* old_block, Block* new_block, Location pc) {
if (pc <= old_block->begin || pc >= old_block->end) {
throw InvalidArgument("Invalid address to split={}", pc);
}
*new_block = Block{
.begin{pc},
.end{old_block->end},
.end_class{old_block->end_class},
.cond{old_block->cond},
.stack{old_block->stack},
.branch_true{old_block->branch_true},
.branch_false{old_block->branch_false},
.function_call{old_block->function_call},
.return_block{old_block->return_block},
.branch_reg{old_block->branch_reg},
.branch_offset{old_block->branch_offset},
.indirect_branches{std::move(old_block->indirect_branches)},
};
*old_block = Block{
.begin{old_block->begin},
.end{pc},
.end_class{EndClass::Branch},
.cond{true},
.stack{std::move(old_block->stack)},
.branch_true{new_block},
.branch_false{nullptr},
.function_call{},
.return_block{},
.branch_reg{},
.branch_offset{},
.indirect_branches{},
};
*new_block = Block{};
new_block->begin = pc;
new_block->end = old_block->end;
new_block->end_class = old_block->end_class,
new_block->cond = old_block->cond;
new_block->stack = old_block->stack;
new_block->branch_true = old_block->branch_true;
new_block->branch_false = old_block->branch_false;
new_block->function_call = old_block->function_call;
new_block->return_block = old_block->return_block;
new_block->branch_reg = old_block->branch_reg;
new_block->branch_offset = old_block->branch_offset;
new_block->indirect_branches = std::move(old_block->indirect_branches);
const Location old_begin{old_block->begin};
Stack old_stack{std::move(old_block->stack)};
*old_block = Block{};
old_block->begin = old_begin;
old_block->end = pc;
old_block->end_class = EndClass::Branch;
old_block->cond = IR::Condition(true);
old_block->stack = old_stack;
old_block->branch_true = new_block;
old_block->branch_false = nullptr;
}
Token OpcodeToken(Opcode opcode) {
@ -141,7 +137,7 @@ std::string NameOf(const Block& block) {
void Stack::Push(Token token, Location target) {
entries.push_back({
.token{token},
.token = token,
.target{target},
});
}
@ -177,24 +173,17 @@ bool Block::Contains(Location pc) const noexcept {
}
Function::Function(ObjectPool<Block>& block_pool, Location start_address)
: entrypoint{start_address}, labels{{
.address{start_address},
.block{block_pool.Create(Block{
.begin{start_address},
.end{start_address},
.end_class{EndClass::Branch},
.cond{true},
.stack{},
.branch_true{nullptr},
.branch_false{nullptr},
.function_call{},
.return_block{},
.branch_reg{},
.branch_offset{},
.indirect_branches{},
})},
.stack{},
}} {}
: entrypoint{start_address} {
Label& label{labels.emplace_back()};
label.address = start_address;
label.block = block_pool.Create(Block{});
label.block->begin = start_address;
label.block->end = start_address;
label.block->end_class = EndClass::Branch;
label.block->cond = IR::Condition(true);
label.block->branch_true = nullptr;
label.block->branch_false = nullptr;
}
CFG::CFG(Environment& env_, ObjectPool<Block>& block_pool_, Location start_address)
: env{env_}, block_pool{block_pool_}, program_start{start_address} {
@ -327,7 +316,8 @@ CFG::AnalysisState CFG::AnalyzeInst(Block* block, FunctionId function_id, Locati
// Insert the function into the list if it doesn't exist
const auto it{std::ranges::find(functions, cal_pc, &Function::entrypoint)};
const bool exists{it != functions.end()};
const FunctionId call_id{exists ? std::distance(functions.begin(), it) : functions.size()};
const FunctionId call_id{exists ? static_cast<size_t>(std::distance(functions.begin(), it))
: functions.size()};
if (!exists) {
functions.emplace_back(block_pool, cal_pc);
}
@ -362,20 +352,14 @@ void CFG::AnalyzeCondInst(Block* block, FunctionId function_id, Location pc,
}
// Create a virtual block and a conditional block
Block* const conditional_block{block_pool.Create()};
Block virtual_block{
.begin{block->begin.Virtual()},
.end{block->begin.Virtual()},
.end_class{EndClass::Branch},
.cond{cond},
.stack{block->stack},
.branch_true{conditional_block},
.branch_false{nullptr},
.function_call{},
.return_block{},
.branch_reg{},
.branch_offset{},
.indirect_branches{},
};
Block virtual_block{};
virtual_block.begin = block->begin.Virtual();
virtual_block.end = block->begin.Virtual();
virtual_block.end_class = EndClass::Branch;
virtual_block.stack = block->stack;
virtual_block.cond = cond;
virtual_block.branch_true = conditional_block;
virtual_block.branch_false = nullptr;
// Save the contents of the visited block in the conditional block
*conditional_block = std::move(*block);
// Impersonate the visited block with a virtual block
@ -444,7 +428,7 @@ CFG::AnalysisState CFG::AnalyzeBRX(Block* block, Location pc, Instruction inst,
if (!is_absolute) {
target += pc.Offset();
}
target += brx_table->branch_offset;
target += static_cast<unsigned int>(brx_table->branch_offset);
target += 8;
targets.push_back(target);
}
@ -455,8 +439,8 @@ CFG::AnalysisState CFG::AnalyzeBRX(Block* block, Location pc, Instruction inst,
for (const u32 target : targets) {
Block* const branch{AddLabel(block, block->stack, target, function_id)};
block->indirect_branches.push_back({
.block{branch},
.address{target},
.block = branch,
.address = target,
});
}
block->cond = IR::Condition{true};
@ -523,23 +507,17 @@ Block* CFG::AddLabel(Block* block, Stack stack, Location pc, FunctionId function
if (label_it != function.labels.end()) {
return label_it->block;
}
Block* const new_block{block_pool.Create(Block{
.begin{pc},
.end{pc},
.end_class{EndClass::Branch},
.cond{true},
.stack{stack},
.branch_true{nullptr},
.branch_false{nullptr},
.function_call{},
.return_block{},
.branch_reg{},
.branch_offset{},
.indirect_branches{},
})};
Block* const new_block{block_pool.Create()};
new_block->begin = pc;
new_block->end = pc;
new_block->end_class = EndClass::Branch;
new_block->cond = IR::Condition(true);
new_block->stack = stack;
new_block->branch_true = nullptr;
new_block->branch_false = nullptr;
function.labels.push_back(Label{
.address{pc},
.block{new_block},
.block = new_block,
.stack{std::move(stack)},
});
return new_block;

10
src/shader_recompiler/frontend/maxwell/decode.cpp
View file

@ -45,7 +45,7 @@ constexpr MaskValue MaskValueFromEncoding(const char* encoding) {
bit >>= 1;
}
}
return MaskValue{.mask{mask}, .value{value}};
return MaskValue{.mask = mask, .value = value};
}
struct InstEncoding {
@ -56,7 +56,7 @@ constexpr std::array UNORDERED_ENCODINGS{
#define INST(name, cute, encode) \
InstEncoding{ \
.mask_value{MaskValueFromEncoding(encode)}, \
.opcode{Opcode::name}, \
.opcode = Opcode::name, \
},
#include "maxwell.inc"
#undef INST
@ -116,9 +116,9 @@ constexpr auto MakeFastLookupTableIndex(size_t index) {
const size_t value{ToFastLookupIndex(encoding.mask_value.value)};
if ((index & mask) == value) {
encodings.at(element) = InstInfo{
.high_mask{static_cast<u16>(encoding.mask_value.mask >> MASK_SHIFT)},
.high_value{static_cast<u16>(encoding.mask_value.value >> MASK_SHIFT)},
.opcode{encoding.opcode},
.high_mask = static_cast<u16>(encoding.mask_value.mask >> MASK_SHIFT),
.high_value = static_cast<u16>(encoding.mask_value.value >> MASK_SHIFT),
.opcode = encoding.opcode,
};
++element;
}

10
src/shader_recompiler/frontend/maxwell/indirect_branch_table_track.cpp
View file

@ -97,11 +97,11 @@ std::optional<IndirectBranchTableInfo> TrackIndirectBranchTable(Environment& env
}
const u32 imnmx_immediate{static_cast<u32>(imnmx.immediate.Value())};
return IndirectBranchTableInfo{
.cbuf_index{cbuf_index},
.cbuf_offset{cbuf_offset},
.num_entries{imnmx_immediate + 1},
.branch_offset{brx_offset},
.branch_reg{brx_reg},
.cbuf_index = cbuf_index,
.cbuf_offset = cbuf_offset,
.num_entries = imnmx_immediate + 1,
.branch_offset = brx_offset,
.branch_reg = brx_reg,
};
}

3
src/shader_recompiler/frontend/maxwell/structured_control_flow.cpp
View file

@ -558,7 +558,6 @@ private:
const Node label{goto_stmt->label};
const u32 label_id{label->id};
const Node label_nested_stmt{FindStatementWithLabel(body, goto_stmt)};
const auto type{label_nested_stmt->type};
Tree loop_body;
loop_body.splice(loop_body.begin(), body, label_nested_stmt, goto_stmt);
@ -566,7 +565,7 @@ private:
Statement* const variable{pool.Create(Variable{}, label_id)};
Statement* const loop_stmt{pool.Create(Loop{}, variable, std::move(loop_body), parent)};
UpdateTreeUp(loop_stmt);
const Node loop_node{body.insert(goto_stmt, *loop_stmt)};
body.insert(goto_stmt, *loop_stmt);
Statement* const new_goto{pool.Create(Goto{}, variable, label, loop_stmt)};
loop_stmt->children.push_front(*new_goto);

6
src/shader_recompiler/frontend/maxwell/translate/impl/double_add.cpp
View file

@ -31,9 +31,9 @@ void DADD(TranslatorVisitor& v, u64 insn, const IR::F64& src_b) {
const IR::F64 op_b{v.ir.FPAbsNeg(src_b, dadd.abs_b != 0, dadd.neg_b != 0)};
const IR::FpControl control{
.no_contraction{true},
.rounding{CastFpRounding(dadd.fp_rounding)},
.fmz_mode{IR::FmzMode::None},
.no_contraction = true,
.rounding = CastFpRounding(dadd.fp_rounding),
.fmz_mode = IR::FmzMode::None,
};
v.D(dadd.dest_reg, v.ir.FPAdd(op_a, op_b, control));

6
src/shader_recompiler/frontend/maxwell/translate/impl/double_fused_multiply_add.cpp
View file

@ -25,9 +25,9 @@ void DFMA(TranslatorVisitor& v, u64 insn, const IR::F64& src_b, const IR::F64& s
const IR::F64 op_c{v.ir.FPAbsNeg(src_c, false, dfma.neg_c != 0)};
const IR::FpControl control{
.no_contraction{true},
.rounding{CastFpRounding(dfma.fp_rounding)},
.fmz_mode{IR::FmzMode::None},
.no_contraction = true,
.rounding = CastFpRounding(dfma.fp_rounding),
.fmz_mode = IR::FmzMode::None,
};
v.D(dfma.dest_reg, v.ir.FPFma(src_a, op_b, op_c, control));

6
src/shader_recompiler/frontend/maxwell/translate/impl/double_multiply.cpp
View file

@ -21,9 +21,9 @@ void DMUL(TranslatorVisitor& v, u64 insn, const IR::F64& src_b) {
const IR::F64 src_a{v.ir.FPAbsNeg(v.D(dmul.src_a_reg), false, dmul.neg != 0)};
const IR::FpControl control{
.no_contraction{true},
.rounding{CastFpRounding(dmul.fp_rounding)},
.fmz_mode{IR::FmzMode::None},
.no_contraction = true,
.rounding = CastFpRounding(dmul.fp_rounding),
.fmz_mode = IR::FmzMode::None,
};
v.D(dmul.dest_reg, v.ir.FPMul(src_a, src_b, control));

6
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_add.cpp
View file

@ -23,9 +23,9 @@ void FADD(TranslatorVisitor& v, u64 insn, bool sat, bool cc, bool ftz, FpRoundin
const IR::F32 op_a{v.ir.FPAbsNeg(v.F(fadd.src_a), abs_a, neg_a)};
const IR::F32 op_b{v.ir.FPAbsNeg(src_b, abs_b, neg_b)};
IR::FpControl control{
.no_contraction{true},
.rounding{CastFpRounding(fp_rounding)},
.fmz_mode{ftz ? IR::FmzMode::FTZ : IR::FmzMode::None},
.no_contraction = true,
.rounding = CastFpRounding(fp_rounding),
.fmz_mode = (ftz ? IR::FmzMode::FTZ : IR::FmzMode::None),
};
IR::F32 value{v.ir.FPAdd(op_a, op_b, control)};
if (sat) {

3
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_compare.cpp
View file

@ -19,8 +19,7 @@ void FCMP(TranslatorVisitor& v, u64 insn, const IR::U32& src_a, const IR::F32& o
} const fcmp{insn};
const IR::F32 zero{v.ir.Imm32(0.0f)};
const IR::F32 neg_zero{v.ir.Imm32(-0.0f)};
const IR::FpControl control{.fmz_mode{fcmp.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None}};
const IR::FpControl control{.fmz_mode = (fcmp.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None)};
const IR::U1 cmp_result{FloatingPointCompare(v.ir, operand, zero, fcmp.compare_op, control)};
const IR::U32 src_reg{v.X(fcmp.src_reg)};
const IR::U32 result{v.ir.Select(cmp_result, src_reg, src_a)};

6
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_compare_and_set.cpp
View file

@ -29,9 +29,9 @@ void FSET(TranslatorVisitor& v, u64 insn, const IR::F32& src_b) {
const IR::F32 op_a{v.ir.FPAbsNeg(v.F(fset.src_a_reg), fset.abs_a != 0, fset.negate_a != 0)};
const IR::F32 op_b = v.ir.FPAbsNeg(src_b, fset.abs_b != 0, fset.negate_b != 0);
const IR::FpControl control{
.no_contraction{false},
.rounding{IR::FpRounding::DontCare},
.fmz_mode{fset.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None},
.no_contraction = false,
.rounding = IR::FpRounding::DontCare,
.fmz_mode = (fset.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None),
};
IR::U1 pred{v.ir.GetPred(fset.pred)};

6
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_conversion_floating_point.cpp
View file

@ -57,9 +57,9 @@ void F2F(TranslatorVisitor& v, u64 insn, const IR::F16F32F64& src_a, bool abs) {
const bool any_fp64{f2f.src_size == FloatFormat::F64 || f2f.dst_size == FloatFormat::F64};
IR::FpControl fp_control{
.no_contraction{false},
.rounding{IR::FpRounding::DontCare},
.fmz_mode{f2f.ftz != 0 && !any_fp64 ? IR::FmzMode::FTZ : IR::FmzMode::None},
.no_contraction = false,
.rounding = IR::FpRounding::DontCare,
.fmz_mode = (f2f.ftz != 0 && !any_fp64 ? IR::FmzMode::FTZ : IR::FmzMode::None),
};
if (f2f.src_size != f2f.dst_size) {
fp_control.rounding = CastFpRounding(f2f.rounding);

11
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
View file

@ -123,9 +123,9 @@ void TranslateF2I(TranslatorVisitor& v, u64 insn, const IR::F16F32F64& src_a) {
fmz_mode = f2i.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None;
}
const IR::FpControl fp_control{
.no_contraction{true},
.rounding{IR::FpRounding::DontCare},
.fmz_mode{fmz_mode},
.no_contraction = true,
.rounding = IR::FpRounding::DontCare,
.fmz_mode = fmz_mode,
};
const IR::F16F32F64 op_a{v.ir.FPAbsNeg(src_a, f2i.abs != 0, f2i.neg != 0)};
const IR::F16F32F64 rounded_value{[&] {
@ -186,14 +186,14 @@ void TranslateF2I(TranslatorVisitor& v, u64 insn, const IR::F16F32F64& src_a) {
} else if (f2i.dest_format == DestFormat::I64) {
handled_special_case = true;
result = IR::U64{
v.ir.Select(v.ir.FPIsNan(op_a), v.ir.Imm64(0x8000'0000'0000'0000ULL), result)};
v.ir.Select(v.ir.FPIsNan(op_a), v.ir.Imm64(0x8000'0000'0000'0000UL), result)};
}
}
if (!handled_special_case && is_signed) {
if (bitsize != 64) {
result = IR::U32{v.ir.Select(v.ir.FPIsNan(op_a), v.ir.Imm32(0U), result)};
} else {
result = IR::U64{v.ir.Select(v.ir.FPIsNan(op_a), v.ir.Imm64(0ULL), result)};
result = IR::U64{v.ir.Select(v.ir.FPIsNan(op_a), v.ir.Imm64(0UL), result)};
}
}
@ -211,6 +211,7 @@ void TranslateF2I(TranslatorVisitor& v, u64 insn, const IR::F16F32F64& src_a) {
void TranslatorVisitor::F2I_reg(u64 insn) {
union {
u64 raw;
F2I base;
BitField<20, 8, IR::Reg> src_reg;
} const f2i{insn};

6
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp
View file

@ -24,9 +24,9 @@ void FFMA(TranslatorVisitor& v, u64 insn, const IR::F32& src_b, const IR::F32& s
const IR::F32 op_b{v.ir.FPAbsNeg(src_b, false, neg_b)};
const IR::F32 op_c{v.ir.FPAbsNeg(src_c, false, neg_c)};
const IR::FpControl fp_control{
.no_contraction{true},
.rounding{CastFpRounding(fp_rounding)},
.fmz_mode{CastFmzMode(fmz_mode)},
.no_contraction = true,
.rounding = CastFpRounding(fp_rounding),
.fmz_mode = CastFmzMode(fmz_mode),
};
IR::F32 value{v.ir.FPFma(op_a, op_b, op_c, fp_control)};
if (fmz_mode == FmzMode::FMZ && !sat) {

6
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_min_max.cpp
View file

@ -27,9 +27,9 @@ void FMNMX(TranslatorVisitor& v, u64 insn, const IR::F32& src_b) {
const IR::F32 op_b{v.ir.FPAbsNeg(src_b, fmnmx.abs_b != 0, fmnmx.negate_b != 0)};
const IR::FpControl control{
.no_contraction{false},
.rounding{IR::FpRounding::DontCare},
.fmz_mode{fmnmx.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None},
.no_contraction = false,
.rounding = IR::FpRounding::DontCare,
.fmz_mode = (fmnmx.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None),
};
IR::F32 max{v.ir.FPMax(op_a, op_b, control)};
IR::F32 min{v.ir.FPMin(op_a, op_b, control)};

8
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_multiply.cpp
View file

@ -64,9 +64,9 @@ void FMUL(TranslatorVisitor& v, u64 insn, const IR::F32& src_b, FmzMode fmz_mode
}
const IR::F32 op_b{v.ir.FPAbsNeg(src_b, false, neg_b)};
const IR::FpControl fp_control{
.no_contraction{true},
.rounding{CastFpRounding(fp_rounding)},
.fmz_mode{CastFmzMode(fmz_mode)},
.no_contraction = true,
.rounding = CastFpRounding(fp_rounding),
.fmz_mode = CastFmzMode(fmz_mode),
};
IR::F32 value{v.ir.FPMul(op_a, op_b, fp_control)};
if (fmz_mode == FmzMode::FMZ && !sat) {
@ -124,4 +124,4 @@ void TranslatorVisitor::FMUL32I(u64 insn) {
fmul32i.sat != 0, fmul32i.cc != 0, false);
}
} // namespace Shader::Maxwell
} // namespace Shader::Maxwell

6
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_set_predicate.cpp
View file

@ -29,9 +29,9 @@ void FSETP(TranslatorVisitor& v, u64 insn, const IR::F32& src_b) {
const IR::F32 op_a{v.ir.FPAbsNeg(v.F(fsetp.src_a_reg), fsetp.abs_a != 0, fsetp.negate_a != 0)};
const IR::F32 op_b = v.ir.FPAbsNeg(src_b, fsetp.abs_b != 0, fsetp.negate_b != 0);
const IR::FpControl control{
.no_contraction{false},
.rounding{IR::FpRounding::DontCare},
.fmz_mode{fsetp.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None},
.no_contraction = false,
.rounding = IR::FpRounding::DontCare,
.fmz_mode = (fsetp.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None),
};
const BooleanOp bop{fsetp.bop};

6
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp
View file

@ -28,9 +28,9 @@ void TranslatorVisitor::FSWZADD(u64 insn) {
const IR::U32 swizzle{ir.Imm32(static_cast<u32>(fswzadd.swizzle))};
const IR::FpControl fp_control{
.no_contraction{false},
.rounding{CastFpRounding(fswzadd.round)},
.fmz_mode{fswzadd.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None},
.no_contraction = false,
.rounding = CastFpRounding(fswzadd.round),
.fmz_mode = (fswzadd.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None),
};
const IR::F32 result{ir.FSwizzleAdd(src_a, src_b, swizzle, fp_control)};

11
src/shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_add.cpp
View file

@ -34,9 +34,9 @@ void HADD2(TranslatorVisitor& v, u64 insn, Merge merge, bool ftz, bool sat, bool
rhs_b = v.ir.FPAbsNeg(rhs_b, abs_b, neg_b);
const IR::FpControl fp_control{
.no_contraction{true},
.rounding{IR::FpRounding::DontCare},
.fmz_mode{ftz ? IR::FmzMode::FTZ : IR::FmzMode::None},
.no_contraction = true,
.rounding = IR::FpRounding::DontCare,
.fmz_mode = (ftz ? IR::FmzMode::FTZ : IR::FmzMode::None),
};
IR::F16F32F64 lhs{v.ir.FPAdd(lhs_a, lhs_b, fp_control)};
IR::F16F32F64 rhs{v.ir.FPAdd(rhs_a, rhs_b, fp_control)};
@ -102,8 +102,9 @@ void TranslatorVisitor::HADD2_imm(u64 insn) {
BitField<20, 9, u64> low;
} const hadd2{insn};
const u32 imm{static_cast<u32>(hadd2.low << 6) | ((hadd2.neg_low != 0 ? 1 : 0) << 15) |
static_cast<u32>(hadd2.high << 22) | ((hadd2.neg_high != 0 ? 1 : 0) << 31)};
const u32 imm{
static_cast<u32>(hadd2.low << 6) | static_cast<u32>((hadd2.neg_low != 0 ? 1 : 0) << 15) |
static_cast<u32>(hadd2.high << 22) | static_cast<u32>((hadd2.neg_high != 0 ? 1 : 0) << 31)};
HADD2(*this, insn, hadd2.sat != 0, false, false, Swizzle::H1_H0, ir.Imm32(imm));
}

11
src/shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_fused_multiply_add.cpp
View file

@ -41,9 +41,9 @@ void HFMA2(TranslatorVisitor& v, u64 insn, Merge merge, Swizzle swizzle_a, bool
rhs_c = v.ir.FPAbsNeg(rhs_c, false, neg_c);
const IR::FpControl fp_control{
.no_contraction{true},
.rounding{IR::FpRounding::DontCare},
.fmz_mode{HalfPrecision2FmzMode(precision)},
.no_contraction = true,
.rounding = IR::FpRounding::DontCare,
.fmz_mode = HalfPrecision2FmzMode(precision),
};
IR::F16F32F64 lhs{v.ir.FPFma(lhs_a, lhs_b, lhs_c, fp_control)};
IR::F16F32F64 rhs{v.ir.FPFma(rhs_a, rhs_b, rhs_c, fp_control)};
@ -143,8 +143,9 @@ void TranslatorVisitor::HFMA2_imm(u64 insn) {
BitField<57, 2, HalfPrecision> precision;
} const hfma2{insn};
const u32 imm{static_cast<u32>(hfma2.low << 6) | ((hfma2.neg_low != 0 ? 1 : 0) << 15) |
static_cast<u32>(hfma2.high << 22) | ((hfma2.neg_high != 0 ? 1 : 0) << 31)};
const u32 imm{
static_cast<u32>(hfma2.low << 6) | static_cast<u32>((hfma2.neg_low != 0 ? 1 : 0) << 15) |
static_cast<u32>(hfma2.high << 22) | static_cast<u32>((hfma2.neg_high != 0 ? 1 : 0) << 31)};
HFMA2(*this, insn, false, hfma2.neg_c != 0, Swizzle::H1_H0, hfma2.swizzle_c, ir.Imm32(imm),
GetReg39(insn), hfma2.saturate != 0, hfma2.precision);

11
src/shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_multiply.cpp
View file

@ -35,9 +35,9 @@ void HMUL2(TranslatorVisitor& v, u64 insn, Merge merge, bool sat, bool abs_a, bo
rhs_b = v.ir.FPAbsNeg(rhs_b, abs_b, neg_b);
const IR::FpControl fp_control{
.no_contraction{true},
.rounding{IR::FpRounding::DontCare},
.fmz_mode{HalfPrecision2FmzMode(precision)},
.no_contraction = true,
.rounding = IR::FpRounding::DontCare,
.fmz_mode = HalfPrecision2FmzMode(precision),
};
IR::F16F32F64 lhs{v.ir.FPMul(lhs_a, lhs_b, fp_control)};
IR::F16F32F64 rhs{v.ir.FPMul(rhs_a, rhs_b, fp_control)};
@ -119,8 +119,9 @@ void TranslatorVisitor::HMUL2_imm(u64 insn) {
BitField<44, 1, u64> abs_a;
} const hmul2{insn};
const u32 imm{static_cast<u32>(hmul2.low << 6) | ((hmul2.neg_low != 0 ? 1 : 0) << 15) |
static_cast<u32>(hmul2.high << 22) | ((hmul2.neg_high != 0 ? 1 : 0) << 31)};
const u32 imm{
static_cast<u32>(hmul2.low << 6) | static_cast<u32>((hmul2.neg_low != 0 ? 1 : 0) << 15) |
static_cast<u32>(hmul2.high << 22) | static_cast<u32>((hmul2.neg_high != 0 ? 1 : 0) << 31)};
HMUL2(*this, insn, hmul2.sat != 0, hmul2.abs_a != 0, hmul2.neg_a != 0, false, false,
Swizzle::H1_H0, ir.Imm32(imm));
}

11
src/shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_set.cpp
View file

@ -41,9 +41,9 @@ void HSET2(TranslatorVisitor& v, u64 insn, const IR::U32& src_b, bool bf, bool f
rhs_b = v.ir.FPAbsNeg(rhs_b, abs_b, neg_b);
const IR::FpControl control{
.no_contraction{false},
.rounding{IR::FpRounding::DontCare},
.fmz_mode{ftz ? IR::FmzMode::FTZ : IR::FmzMode::None},
.no_contraction = false,
.rounding = IR::FpRounding::DontCare,
.fmz_mode = (ftz ? IR::FmzMode::FTZ : IR::FmzMode::None),
};
IR::U1 pred{v.ir.GetPred(hset2.pred)};
@ -106,8 +106,9 @@ void TranslatorVisitor::HSET2_imm(u64 insn) {
BitField<20, 9, u64> low;
} const hset2{insn};
const u32 imm{static_cast<u32>(hset2.low << 6) | ((hset2.neg_low != 0 ? 1 : 0) << 15) |
static_cast<u32>(hset2.high << 22) | ((hset2.neg_high != 0 ? 1 : 0) << 31)};
const u32 imm{
static_cast<u32>(hset2.low << 6) | static_cast<u32>((hset2.neg_low != 0 ? 1 : 0) << 15) |
static_cast<u32>(hset2.high << 22) | static_cast<u32>((hset2.neg_high != 0 ? 1 : 0) << 31)};
HSET2(*this, insn, ir.Imm32(imm), hset2.bf != 0, hset2.ftz != 0, false, false, hset2.compare_op,
Swizzle::H1_H0);

12
src/shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_set_predicate.cpp
View file

@ -43,9 +43,9 @@ void HSETP2(TranslatorVisitor& v, u64 insn, const IR::U32& src_b, bool neg_b, bo
rhs_b = v.ir.FPAbsNeg(rhs_b, abs_b, neg_b);
const IR::FpControl control{
.no_contraction{false},
.rounding{IR::FpRounding::DontCare},
.fmz_mode{hsetp2.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None},
.no_contraction = false,
.rounding = IR::FpRounding::DontCare,
.fmz_mode = (hsetp2.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None),
};
IR::U1 pred{v.ir.GetPred(hsetp2.pred)};
@ -106,8 +106,10 @@ void TranslatorVisitor::HSETP2_imm(u64 insn) {
BitField<20, 9, u64> low;
} const hsetp2{insn};
const u32 imm{static_cast<u32>(hsetp2.low << 6) | ((hsetp2.neg_low != 0 ? 1 : 0) << 15) |
static_cast<u32>(hsetp2.high << 22) | ((hsetp2.neg_high != 0 ? 1 : 0) << 31)};
const u32 imm{static_cast<u32>(hsetp2.low << 6) |
static_cast<u32>((hsetp2.neg_low != 0 ? 1 : 0) << 15) |
static_cast<u32>(hsetp2.high << 22) |
static_cast<u32>((hsetp2.neg_high != 0 ? 1 : 0) << 31)};
HSETP2(*this, insn, ir.Imm32(imm), false, false, Swizzle::H1_H0, hsetp2.compare_op,
hsetp2.h_and != 0);

8
src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
View file

@ -49,7 +49,7 @@ void TranslatorVisitor::L(IR::Reg dest_reg, const IR::U64& value) {
}
const IR::Value result{ir.UnpackUint2x32(value)};
for (int i = 0; i < 2; i++) {
X(dest_reg + i, IR::U32{ir.CompositeExtract(result, i)});
X(dest_reg + i, IR::U32{ir.CompositeExtract(result, static_cast<size_t>(i))});
}
}
@ -63,7 +63,7 @@ void TranslatorVisitor::D(IR::Reg dest_reg, const IR::F64& value) {
}
const IR::Value result{ir.UnpackDouble2x32(value)};
for (int i = 0; i < 2; i++) {
X(dest_reg + i, IR::U32{ir.CompositeExtract(result, i)});
X(dest_reg + i, IR::U32{ir.CompositeExtract(result, static_cast<size_t>(i))});
}
}
@ -156,7 +156,7 @@ IR::F64 TranslatorVisitor::GetDoubleCbuf(u64 insn) {
const auto [binding, offset_value]{CbufAddr(insn)};
const bool unaligned{cbuf.unaligned != 0};
const u32 offset{offset_value.U32()};
const IR::Value addr{unaligned ? offset | 4 : (offset & ~7) | 4};
const IR::Value addr{unaligned ? offset | 4u : (offset & ~7u) | 4u};
const IR::U32 value{ir.GetCbuf(binding, IR::U32{addr})};
const IR::U32 lower_bits{CbufLowerBits(ir, unaligned, binding, offset)};
@ -200,7 +200,7 @@ IR::F32 TranslatorVisitor::GetFloatImm20(u64 insn) {
BitField<20, 19, u64> value;
BitField<56, 1, u64> is_negative;
} const imm{insn};
const u32 sign_bit{imm.is_negative != 0 ? (1ULL << 31) : 0};
const u32 sign_bit{static_cast<u32>(imm.is_negative != 0 ? (1ULL << 31) : 0)};
const u32 value{static_cast<u32>(imm.value) << 12};
return ir.Imm32(Common::BitCast<f32>(value | sign_bit));
}

1
src/shader_recompiler/frontend/maxwell/translate/impl/integer_add.cpp
View file

@ -68,7 +68,6 @@ void IADD(TranslatorVisitor& v, u64 insn, IR::U32 op_b) {
} const iadd{insn};
const bool po{iadd.three_for_po == 3};
const bool neg_a{!po && iadd.neg_a != 0};
if (!po && iadd.neg_b != 0) {
op_b = v.ir.INeg(op_b);
}

4
src/shader_recompiler/frontend/maxwell/translate/impl/integer_floating_point_conversion.cpp
View file

@ -131,7 +131,7 @@ void I2F(TranslatorVisitor& v, u64 insn, IR::U32U64 src) {
}
const IR::Value vector{v.ir.UnpackDouble2x32(value)};
for (int i = 0; i < 2; ++i) {
v.X(i2f.dest_reg + i, IR::U32{v.ir.CompositeExtract(vector, i)});
v.X(i2f.dest_reg + i, IR::U32{v.ir.CompositeExtract(vector, static_cast<size_t>(i))});
}
break;
}
@ -170,4 +170,4 @@ void TranslatorVisitor::I2F_imm(u64 insn) {
}
}
} // namespace Shader::Maxwell
} // namespace Shader::Maxwell

2
src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp
View file

@ -50,7 +50,7 @@ void TranslatorVisitor::LDC(u64 insn) {
}
const IR::Value vector{ir.GetCbuf(index, offset, 64, false)};
for (int i = 0; i < 2; ++i) {
X(ldc.dest_reg + i, IR::U32{ir.CompositeExtract(vector, i)});
X(ldc.dest_reg + i, IR::U32{ir.CompositeExtract(vector, static_cast<size_t>(i))});
}
break;
}

9
src/shader_recompiler/frontend/maxwell/translate/impl/load_store_local_shared.cpp
View file

@ -40,7 +40,6 @@ std::pair<int, bool> GetSize(u64 insn) {
BitField<48, 3, Size> size;
} const encoding{insn};
const Size nnn = encoding.size;
switch (encoding.size) {
case Size::U8:
return {8, false};
@ -99,7 +98,7 @@ void TranslatorVisitor::LDL(u64 insn) {
case 32:
case 64:
case 128:
if (!IR::IsAligned(dest, bit_size / 32)) {
if (!IR::IsAligned(dest, static_cast<size_t>(bit_size / 32))) {
throw NotImplementedException("Unaligned destination register {}", dest);
}
X(dest, ir.LoadLocal(word_offset));
@ -123,11 +122,11 @@ void TranslatorVisitor::LDS(u64 insn) {
break;
case 64:
case 128:
if (!IR::IsAligned(dest, bit_size / 32)) {
if (!IR::IsAligned(dest, static_cast<size_t>(bit_size / 32))) {
throw NotImplementedException("Unaligned destination register {}", dest);
}
for (int element = 0; element < bit_size / 32; ++element) {
X(dest + element, IR::U32{ir.CompositeExtract(value, element)});
X(dest + element, IR::U32{ir.CompositeExtract(value, static_cast<size_t>(element))});
}
break;
}
@ -156,7 +155,7 @@ void TranslatorVisitor::STL(u64 insn) {
case 32:
case 64:
case 128:
if (!IR::IsAligned(reg, bit_size / 32)) {
if (!IR::IsAligned(reg, static_cast<size_t>(bit_size / 32))) {
throw NotImplementedException("Unaligned source register");
}
ir.WriteLocal(word_offset, src);

4
src/shader_recompiler/frontend/maxwell/translate/impl/load_store_memory.cpp
View file

@ -114,7 +114,7 @@ void TranslatorVisitor::LDG(u64 insn) {
}
const IR::Value vector{ir.LoadGlobal64(address)};
for (int i = 0; i < 2; ++i) {
X(dest_reg + i, IR::U32{ir.CompositeExtract(vector, i)});
X(dest_reg + i, IR::U32{ir.CompositeExtract(vector, static_cast<size_t>(i))});
}
break;
}
@ -125,7 +125,7 @@ void TranslatorVisitor::LDG(u64 insn) {
}
const IR::Value vector{ir.LoadGlobal128(address)};
for (int i = 0; i < 4; ++i) {
X(dest_reg + i, IR::U32{ir.CompositeExtract(vector, i)});
X(dest_reg + i, IR::U32{ir.CompositeExtract(vector, static_cast<size_t>(i))});
}
break;
}

2
src/shader_recompiler/frontend/maxwell/translate/impl/texture_fetch.cpp
View file

@ -199,7 +199,7 @@ void Impl(TranslatorVisitor& v, u64 insn, bool aoffi, Blod blod, bool lc,
if (tex.dc != 0) {
value = element < 3 ? IR::F32{sample} : v.ir.Imm32(1.0f);
} else {
value = IR::F32{v.ir.CompositeExtract(sample, element)};
value = IR::F32{v.ir.CompositeExtract(sample, static_cast<size_t>(element))};
}
v.F(dest_reg, value);
++dest_reg;

2
src/shader_recompiler/frontend/maxwell/translate/impl/texture_fetch_swizzled.cpp
View file

@ -53,7 +53,7 @@ constexpr std::array RGBA_LUT{
R | G | B | A, //
};
void CheckAlignment(IR::Reg reg, int alignment) {
void CheckAlignment(IR::Reg reg, size_t alignment) {
if (!IR::IsAligned(reg, alignment)) {
throw NotImplementedException("Unaligned source register {}", reg);
}

2
src/shader_recompiler/frontend/maxwell/translate/impl/texture_gather_swizzled.cpp
View file

@ -37,7 +37,7 @@ union Encoding {
BitField<36, 13, u64> cbuf_offset;
};
void CheckAlignment(IR::Reg reg, int alignment) {
void CheckAlignment(IR::Reg reg, size_t alignment) {
if (!IR::IsAligned(reg, alignment)) {
throw NotImplementedException("Unaligned source register {}", reg);
}

2
src/shader_recompiler/frontend/maxwell/translate/impl/texture_load_swizzled.cpp
View file

@ -56,7 +56,7 @@ union Encoding {
BitField<53, 4, u64> encoding;
};
void CheckAlignment(IR::Reg reg, int alignment) {
void CheckAlignment(IR::Reg reg, size_t alignment) {
if (!IR::IsAligned(reg, alignment)) {
throw NotImplementedException("Unaligned source register {}", reg);
}

2
src/shader_recompiler/frontend/maxwell/translate/impl/texture_query.cpp
View file

@ -54,7 +54,7 @@ void Impl(TranslatorVisitor& v, u64 insn, std::optional<u32> cbuf_offset) {
if (((txq.mask >> element) & 1) == 0) {
continue;
}
v.X(dest_reg, IR::U32{v.ir.CompositeExtract(query, element)});
v.X(dest_reg, IR::U32{v.ir.CompositeExtract(query, static_cast<size_t>(element))});
++dest_reg;
}
}

1
src/shader_recompiler/frontend/maxwell/translate/impl/video_set_predicate.cpp
View file

@ -69,7 +69,6 @@ void TranslatorVisitor::VSETP(u64 insn) {
const IR::U32 src_b{is_b_imm ? ir.Imm32(static_cast<u32>(vsetp.src_b_imm)) : GetReg20(insn)};
const u32 a_selector{static_cast<u32>(vsetp.src_a_selector)};
const u32 b_selector{is_b_imm ? 0U : static_cast<u32>(vsetp.src_b_selector)};
const VideoWidth a_width{vsetp.src_a_width};
const VideoWidth b_width{GetVideoSourceWidth(vsetp.src_b_width, is_b_imm)};