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Remove references to PICA and rasterizers in video_core

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This commit is contained in:
James Rowe 2018-01-11 20:07:44 -07:00
parent ebf9a784a9
commit 1d28b2e142
77 changed files with 4 additions and 16444 deletions
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47
src/core/hw/aes/arithmetic128.cpp
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@ -1,47 +0,0 @@
// Copyright 2017 Citra Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include <algorithm>
#include <functional>
#include "core/hw/aes/arithmetic128.h"
namespace HW {
namespace AES {
AESKey Lrot128(const AESKey& in, u32 rot) {
AESKey out;
rot %= 128;
const u32 byte_shift = rot / 8;
const u32 bit_shift = rot % 8;
for (u32 i = 0; i < 16; i++) {
const u32 wrap_index_a = (i + byte_shift) % 16;
const u32 wrap_index_b = (i + byte_shift + 1) % 16;
out[i] = ((in[wrap_index_a] << bit_shift) | (in[wrap_index_b] >> (8 - bit_shift))) & 0xFF;
}
return out;
}
AESKey Add128(const AESKey& a, const AESKey& b) {
AESKey out;
u32 carry = 0;
u32 sum = 0;
for (int i = 15; i >= 0; i--) {
sum = a[i] + b[i] + carry;
carry = sum >> 8;
out[i] = static_cast<u8>(sum & 0xff);
}
return out;
}
AESKey Xor128(const AESKey& a, const AESKey& b) {
AESKey out;
std::transform(a.cbegin(), a.cend(), b.cbegin(), out.begin(), std::bit_xor<>());
return out;
}
} // namespace AES
} // namespace HW

17
src/core/hw/aes/arithmetic128.h
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// Copyright 2017 Citra Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#pragma once
#include "common/common_types.h"
#include "core/hw/aes/key.h"
namespace HW {
namespace AES {
AESKey Lrot128(const AESKey& in, u32 rot);
AESKey Add128(const AESKey& a, const AESKey& b);
AESKey Xor128(const AESKey& a, const AESKey& b);
} // namspace AES
} // namespace HW

40
src/core/hw/aes/ccm.h
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// Copyright 2017 Citra Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#pragma once
#include <array>
#include <cstddef>
#include <vector>
#include "common/common_types.h"
namespace HW {
namespace AES {
constexpr size_t CCM_NONCE_SIZE = 12;
constexpr size_t CCM_MAC_SIZE = 16;
using CCMNonce = std::array<u8, CCM_NONCE_SIZE>;
/**
* Encrypts and adds a MAC to the given data using AES-CCM algorithm.
* @param pdata The plain text data to encrypt
* @param nonce The nonce data to use for encryption
* @param slot_id The slot ID of the key to use for encryption
* @returns a vector of u8 containing the encrypted data with MAC at the end
*/
std::vector<u8> EncryptSignCCM(const std::vector<u8>& pdata, const CCMNonce& nonce, size_t slot_id);
/**
* Decrypts and verify the MAC of the given data using AES-CCM algorithm.
* @param cipher The cipher text data to decrypt, with MAC at the end to verify
* @param nonce The nonce data to use for decryption
* @param slot_id The slot ID of the key to use for decryption
* @returns a vector of u8 containing the decrypted data; an empty vector if the verification fails
*/
std::vector<u8> DecryptVerifyCCM(const std::vector<u8>& cipher, const CCMNonce& nonce,
size_t slot_id);
} // namespace AES
} // namespace HW

173
src/core/hw/aes/key.cpp
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@ -1,173 +0,0 @@
// Copyright 2017 Citra Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include <algorithm>
#include <exception>
#include <sstream>
#include <boost/optional.hpp>
#include "common/common_paths.h"
#include "common/file_util.h"
#include "common/logging/log.h"
#include "common/string_util.h"
#include "core/hw/aes/arithmetic128.h"
#include "core/hw/aes/key.h"
namespace HW {
namespace AES {
namespace {
boost::optional<AESKey> generator_constant;
struct KeySlot {
boost::optional<AESKey> x;
boost::optional<AESKey> y;
boost::optional<AESKey> normal;
void SetKeyX(const AESKey& key) {
x = key;
if (y && generator_constant) {
GenerateNormalKey();
}
}
void SetKeyY(const AESKey& key) {
y = key;
if (x && generator_constant) {
GenerateNormalKey();
}
}
void SetNormalKey(const AESKey& key) {
normal = key;
}
void GenerateNormalKey() {
normal = Lrot128(Add128(Xor128(Lrot128(*x, 2), *y), *generator_constant), 87);
}
void Clear() {
x.reset();
y.reset();
normal.reset();
}
};
std::array<KeySlot, KeySlotID::MaxKeySlotID> key_slots;
void ClearAllKeys() {
for (KeySlot& slot : key_slots) {
slot.Clear();
}
generator_constant.reset();
}
AESKey HexToKey(const std::string& hex) {
if (hex.size() < 32) {
throw std::invalid_argument("hex string is too short");
}
AESKey key;
for (size_t i = 0; i < key.size(); ++i) {
key[i] = static_cast<u8>(std::stoi(hex.substr(i * 2, 2), 0, 16));
}
return key;
}
void LoadPresetKeys() {
const std::string filepath = FileUtil::GetUserPath(D_SYSDATA_IDX) + AES_KEYS;
FileUtil::CreateFullPath(filepath); // Create path if not already created
std::ifstream file;
OpenFStream(file, filepath, std::ios_base::in);
if (!file) {
return;
}
while (!file.eof()) {
std::string line;
std::getline(file, line);
std::vector<std::string> parts;
Common::SplitString(line, '=', parts);
if (parts.size() != 2) {
LOG_ERROR(HW_AES, "Failed to parse %s", line.c_str());
continue;
}
const std::string& name = parts[0];
AESKey key;
try {
key = HexToKey(parts[1]);
} catch (const std::logic_error& e) {
LOG_ERROR(HW_AES, "Invalid key %s: %s", parts[1].c_str(), e.what());
continue;
}
if (name == "generator") {
generator_constant = key;
continue;
}
size_t slot_id;
char key_type;
if (std::sscanf(name.c_str(), "slot0x%zXKey%c", &slot_id, &key_type) != 2) {
LOG_ERROR(HW_AES, "Invalid key name %s", name.c_str());
continue;
}
if (slot_id >= MaxKeySlotID) {
LOG_ERROR(HW_AES, "Out of range slot ID 0x%zX", slot_id);
continue;
}
switch (key_type) {
case 'X':
key_slots.at(slot_id).SetKeyX(key);
break;
case 'Y':
key_slots.at(slot_id).SetKeyY(key);
break;
case 'N':
key_slots.at(slot_id).SetNormalKey(key);
break;
default:
LOG_ERROR(HW_AES, "Invalid key type %c", key_type);
break;
}
}
}
} // namespace
void InitKeys() {
ClearAllKeys();
LoadPresetKeys();
}
void SetGeneratorConstant(const AESKey& key) {
generator_constant = key;
}
void SetKeyX(size_t slot_id, const AESKey& key) {
key_slots.at(slot_id).SetKeyX(key);
}
void SetKeyY(size_t slot_id, const AESKey& key) {
key_slots.at(slot_id).SetKeyY(key);
}
void SetNormalKey(size_t slot_id, const AESKey& key) {
key_slots.at(slot_id).SetNormalKey(key);
}
bool IsNormalKeyAvailable(size_t slot_id) {
return key_slots.at(slot_id).normal.is_initialized();
}
AESKey GetNormalKey(size_t slot_id) {
return key_slots.at(slot_id).normal.value_or(AESKey{});
}
} // namespace AES
} // namespace HW

37
src/core/hw/aes/key.h
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// Copyright 2017 Citra Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#pragma once
#include <array>
#include <cstddef>
#include "common/common_types.h"
namespace HW {
namespace AES {
enum KeySlotID : size_t {
// AES Keyslot used to generate the UDS data frame CCMP key.
UDSDataKey = 0x2D,
APTWrap = 0x31,
MaxKeySlotID = 0x40,
};
constexpr size_t AES_BLOCK_SIZE = 16;
using AESKey = std::array<u8, AES_BLOCK_SIZE>;
void InitKeys();
void SetGeneratorConstant(const AESKey& key);
void SetKeyX(size_t slot_id, const AESKey& key);
void SetKeyY(size_t slot_id, const AESKey& key);
void SetNormalKey(size_t slot_id, const AESKey& key);
bool IsNormalKeyAvailable(size_t slot_id);
AESKey GetNormalKey(size_t slot_id);
} // namspace AES
} // namespace HW

573
src/core/hw/gpu.cpp
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// Copyright 2014 Citra Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include <cstring>
#include <numeric>
#include <type_traits>
#include "common/alignment.h"
#include "common/color.h"
#include "common/common_types.h"
#include "common/logging/log.h"
#include "common/microprofile.h"
#include "common/vector_math.h"
#include "core/core_timing.h"
#include "core/hle/service/gsp_gpu.h"
#include "core/hw/gpu.h"
#include "core/hw/hw.h"
#include "core/memory.h"
#include "core/tracer/recorder.h"
#include "video_core/command_processor.h"
#include "video_core/debug_utils/debug_utils.h"
#include "video_core/rasterizer_interface.h"
#include "video_core/renderer_base.h"
#include "video_core/utils.h"
#include "video_core/video_core.h"
namespace GPU {
Regs g_regs;
/// 268MHz CPU clocks / 60Hz frames per second
const u64 frame_ticks = static_cast<u64>(BASE_CLOCK_RATE / SCREEN_REFRESH_RATE);
/// Event id for CoreTiming
static CoreTiming::EventType* vblank_event;
template <typename T>
inline void Read(T& var, const u32 raw_addr) {
u32 addr = raw_addr - HW::VADDR_GPU;
u32 index = addr / 4;
// Reads other than u32 are untested, so I'd rather have them abort than silently fail
if (index >= Regs::NumIds() || !std::is_same<T, u32>::value) {
LOG_ERROR(HW_GPU, "unknown Read%lu @ 0x%08X", sizeof(var) * 8, addr);
return;
}
var = g_regs[addr / 4];
}
static Math::Vec4<u8> DecodePixel(Regs::PixelFormat input_format, const u8* src_pixel) {
switch (input_format) {
case Regs::PixelFormat::RGBA8:
return Color::DecodeRGBA8(src_pixel);
case Regs::PixelFormat::RGB8:
return Color::DecodeRGB8(src_pixel);
case Regs::PixelFormat::RGB565:
return Color::DecodeRGB565(src_pixel);
case Regs::PixelFormat::RGB5A1:
return Color::DecodeRGB5A1(src_pixel);
case Regs::PixelFormat::RGBA4:
return Color::DecodeRGBA4(src_pixel);
default:
LOG_ERROR(HW_GPU, "Unknown source framebuffer format %x", input_format);
return {0, 0, 0, 0};
}
}
MICROPROFILE_DEFINE(GPU_DisplayTransfer, "GPU", "DisplayTransfer", MP_RGB(100, 100, 255));
MICROPROFILE_DEFINE(GPU_CmdlistProcessing, "GPU", "Cmdlist Processing", MP_RGB(100, 255, 100));
static void MemoryFill(const Regs::MemoryFillConfig& config) {
const PAddr start_addr = config.GetStartAddress();
const PAddr end_addr = config.GetEndAddress();
// TODO: do hwtest with these cases
if (!Memory::IsValidPhysicalAddress(start_addr)) {
LOG_CRITICAL(HW_GPU, "invalid start address 0x%08X", start_addr);
return;
}
if (!Memory::IsValidPhysicalAddress(end_addr)) {
LOG_CRITICAL(HW_GPU, "invalid end address 0x%08X", end_addr);
return;
}
if (end_addr <= start_addr) {
LOG_CRITICAL(HW_GPU, "invalid memory range from 0x%08X to 0x%08X", start_addr, end_addr);
return;
}
u8* start = Memory::GetPhysicalPointer(start_addr);
u8* end = Memory::GetPhysicalPointer(end_addr);
// TODO: Consider always accelerating and returning vector of
// regions that the accelerated fill did not cover to
// reduce/eliminate the fill that the cpu has to do.
// This would also mean that the flush below is not needed.
// Fill should first flush all surfaces that touch but are
// not completely within the fill range.
// Then fill all completely covered surfaces, and return the
// regions that were between surfaces or within the touching
// ones for cpu to manually fill here.
if (VideoCore::g_renderer->Rasterizer()->AccelerateFill(config))
return;
Memory::RasterizerFlushAndInvalidateRegion(config.GetStartAddress(),
config.GetEndAddress() - config.GetStartAddress());
if (config.fill_24bit) {
// fill with 24-bit values
for (u8* ptr = start; ptr < end; ptr += 3) {
ptr[0] = config.value_24bit_r;
ptr[1] = config.value_24bit_g;
ptr[2] = config.value_24bit_b;
}
} else if (config.fill_32bit) {
// fill with 32-bit values
if (end > start) {
u32 value = config.value_32bit;
size_t len = (end - start) / sizeof(u32);
for (size_t i = 0; i < len; ++i)
memcpy(&start[i * sizeof(u32)], &value, sizeof(u32));
}
} else {
// fill with 16-bit values
u16 value_16bit = config.value_16bit.Value();
for (u8* ptr = start; ptr < end; ptr += sizeof(u16))
memcpy(ptr, &value_16bit, sizeof(u16));
}
}
static void DisplayTransfer(const Regs::DisplayTransferConfig& config) {
const PAddr src_addr = config.GetPhysicalInputAddress();
const PAddr dst_addr = config.GetPhysicalOutputAddress();
// TODO: do hwtest with these cases
if (!Memory::IsValidPhysicalAddress(src_addr)) {
LOG_CRITICAL(HW_GPU, "invalid input address 0x%08X", src_addr);
return;
}
if (!Memory::IsValidPhysicalAddress(dst_addr)) {
LOG_CRITICAL(HW_GPU, "invalid output address 0x%08X", dst_addr);
return;
}
if (config.input_width == 0) {
LOG_CRITICAL(HW_GPU, "zero input width");
return;
}
if (config.input_height == 0) {
LOG_CRITICAL(HW_GPU, "zero input height");
return;
}
if (config.output_width == 0) {
LOG_CRITICAL(HW_GPU, "zero output width");
return;
}
if (config.output_height == 0) {
LOG_CRITICAL(HW_GPU, "zero output height");
return;
}
if (VideoCore::g_renderer->Rasterizer()->AccelerateDisplayTransfer(config))
return;
u8* src_pointer = Memory::GetPhysicalPointer(src_addr);
u8* dst_pointer = Memory::GetPhysicalPointer(dst_addr);
if (config.scaling > config.ScaleXY) {
LOG_CRITICAL(HW_GPU, "Unimplemented display transfer scaling mode %u",
config.scaling.Value());
UNIMPLEMENTED();
return;
}
if (config.input_linear && config.scaling != config.NoScale) {
LOG_CRITICAL(HW_GPU, "Scaling is only implemented on tiled input");
UNIMPLEMENTED();
return;
}
int horizontal_scale = config.scaling != config.NoScale ? 1 : 0;
int vertical_scale = config.scaling == config.ScaleXY ? 1 : 0;
u32 output_width = config.output_width >> horizontal_scale;
u32 output_height = config.output_height >> vertical_scale;
u32 input_size =
config.input_width * config.input_height * GPU::Regs::BytesPerPixel(config.input_format);
u32 output_size = output_width * output_height * GPU::Regs::BytesPerPixel(config.output_format);
Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(), input_size);
Memory::RasterizerFlushAndInvalidateRegion(config.GetPhysicalOutputAddress(), output_size);
for (u32 y = 0; y < output_height; ++y) {
for (u32 x = 0; x < output_width; ++x) {
Math::Vec4<u8> src_color;
// Calculate the [x,y] position of the input image
// based on the current output position and the scale
u32 input_x = x << horizontal_scale;
u32 input_y = y << vertical_scale;
u32 output_y;
if (config.flip_vertically) {
// Flip the y value of the output data,
// we do this after calculating the [x,y] position of the input image
// to account for the scaling options.
output_y = output_height - y - 1;
} else {
output_y = y;
}
u32 dst_bytes_per_pixel = GPU::Regs::BytesPerPixel(config.output_format);
u32 src_bytes_per_pixel = GPU::Regs::BytesPerPixel(config.input_format);
u32 src_offset;
u32 dst_offset;
if (config.input_linear) {
if (!config.dont_swizzle) {
// Interpret the input as linear and the output as tiled
u32 coarse_y = output_y & ~7;
u32 stride = output_width * dst_bytes_per_pixel;
src_offset = (input_x + input_y * config.input_width) * src_bytes_per_pixel;
dst_offset = VideoCore::GetMortonOffset(x, output_y, dst_bytes_per_pixel) +
coarse_y * stride;
} else {
// Both input and output are linear
src_offset = (input_x + input_y * config.input_width) * src_bytes_per_pixel;
dst_offset = (x + output_y * output_width) * dst_bytes_per_pixel;
}
} else {
if (!config.dont_swizzle) {
// Interpret the input as tiled and the output as linear
u32 coarse_y = input_y & ~7;
u32 stride = config.input_width * src_bytes_per_pixel;
src_offset = VideoCore::GetMortonOffset(input_x, input_y, src_bytes_per_pixel) +
coarse_y * stride;
dst_offset = (x + output_y * output_width) * dst_bytes_per_pixel;
} else {
// Both input and output are tiled
u32 out_coarse_y = output_y & ~7;
u32 out_stride = output_width * dst_bytes_per_pixel;
u32 in_coarse_y = input_y & ~7;
u32 in_stride = config.input_width * src_bytes_per_pixel;
src_offset = VideoCore::GetMortonOffset(input_x, input_y, src_bytes_per_pixel) +
in_coarse_y * in_stride;
dst_offset = VideoCore::GetMortonOffset(x, output_y, dst_bytes_per_pixel) +
out_coarse_y * out_stride;
}
}
const u8* src_pixel = src_pointer + src_offset;
src_color = DecodePixel(config.input_format, src_pixel);
if (config.scaling == config.ScaleX) {
Math::Vec4<u8> pixel =
DecodePixel(config.input_format, src_pixel + src_bytes_per_pixel);
src_color = ((src_color + pixel) / 2).Cast<u8>();
} else if (config.scaling == config.ScaleXY) {
Math::Vec4<u8> pixel1 =
DecodePixel(config.input_format, src_pixel + 1 * src_bytes_per_pixel);
Math::Vec4<u8> pixel2 =
DecodePixel(config.input_format, src_pixel + 2 * src_bytes_per_pixel);
Math::Vec4<u8> pixel3 =
DecodePixel(config.input_format, src_pixel + 3 * src_bytes_per_pixel);
src_color = (((src_color + pixel1) + (pixel2 + pixel3)) / 4).Cast<u8>();
}
u8* dst_pixel = dst_pointer + dst_offset;
switch (config.output_format) {
case Regs::PixelFormat::RGBA8:
Color::EncodeRGBA8(src_color, dst_pixel);
break;
case Regs::PixelFormat::RGB8:
Color::EncodeRGB8(src_color, dst_pixel);
break;
case Regs::PixelFormat::RGB565:
Color::EncodeRGB565(src_color, dst_pixel);
break;
case Regs::PixelFormat::RGB5A1:
Color::EncodeRGB5A1(src_color, dst_pixel);
break;
case Regs::PixelFormat::RGBA4:
Color::EncodeRGBA4(src_color, dst_pixel);
break;
default:
LOG_ERROR(HW_GPU, "Unknown destination framebuffer format %x",
config.output_format.Value());
break;
}
}
}
}
static void TextureCopy(const Regs::DisplayTransferConfig& config) {
const PAddr src_addr = config.GetPhysicalInputAddress();
const PAddr dst_addr = config.GetPhysicalOutputAddress();
// TODO: do hwtest with invalid addresses
if (!Memory::IsValidPhysicalAddress(src_addr)) {
LOG_CRITICAL(HW_GPU, "invalid input address 0x%08X", src_addr);
return;
}
if (!Memory::IsValidPhysicalAddress(dst_addr)) {
LOG_CRITICAL(HW_GPU, "invalid output address 0x%08X", dst_addr);
return;
}
if (VideoCore::g_renderer->Rasterizer()->AccelerateTextureCopy(config))
return;
u8* src_pointer = Memory::GetPhysicalPointer(src_addr);
u8* dst_pointer = Memory::GetPhysicalPointer(dst_addr);
u32 remaining_size = Common::AlignDown(config.texture_copy.size, 16);
if (remaining_size == 0) {
LOG_CRITICAL(HW_GPU, "zero size. Real hardware freezes on this.");
return;
}
u32 input_gap = config.texture_copy.input_gap * 16;
u32 output_gap = config.texture_copy.output_gap * 16;
// Zero gap means contiguous input/output even if width = 0. To avoid infinite loop below, width
// is assigned with the total size if gap = 0.
u32 input_width = input_gap == 0 ? remaining_size : config.texture_copy.input_width * 16;
u32 output_width = output_gap == 0 ? remaining_size : config.texture_copy.output_width * 16;
if (input_width == 0) {
LOG_CRITICAL(HW_GPU, "zero input width. Real hardware freezes on this.");
return;
}
if (output_width == 0) {
LOG_CRITICAL(HW_GPU, "zero output width. Real hardware freezes on this.");
return;
}
size_t contiguous_input_size =
config.texture_copy.size / input_width * (input_width + input_gap);
Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(),
static_cast<u32>(contiguous_input_size));
size_t contiguous_output_size =
config.texture_copy.size / output_width * (output_width + output_gap);
Memory::RasterizerFlushAndInvalidateRegion(config.GetPhysicalOutputAddress(),
static_cast<u32>(contiguous_output_size));
u32 remaining_input = input_width;
u32 remaining_output = output_width;
while (remaining_size > 0) {
u32 copy_size = std::min({remaining_input, remaining_output, remaining_size});
std::memcpy(dst_pointer, src_pointer, copy_size);
src_pointer += copy_size;
dst_pointer += copy_size;
remaining_input -= copy_size;
remaining_output -= copy_size;
remaining_size -= copy_size;
if (remaining_input == 0) {
remaining_input = input_width;
src_pointer += input_gap;
}
if (remaining_output == 0) {
remaining_output = output_width;
dst_pointer += output_gap;
}
}
}
template <typename T>
inline void Write(u32 addr, const T data) {
addr -= HW::VADDR_GPU;
u32 index = addr / 4;
// Writes other than u32 are untested, so I'd rather have them abort than silently fail
if (index >= Regs::NumIds() || !std::is_same<T, u32>::value) {
LOG_ERROR(HW_GPU, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, addr);
return;
}
g_regs[index] = static_cast<u32>(data);
switch (index) {
// Memory fills are triggered once the fill value is written.
case GPU_REG_INDEX_WORKAROUND(memory_fill_config[0].trigger, 0x00004 + 0x3):
case GPU_REG_INDEX_WORKAROUND(memory_fill_config[1].trigger, 0x00008 + 0x3): {
const bool is_second_filler = (index != GPU_REG_INDEX(memory_fill_config[0].trigger));
auto& config = g_regs.memory_fill_config[is_second_filler];
if (config.trigger) {
MemoryFill(config);
LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(),
config.GetEndAddress());
// It seems that it won't signal interrupt if "address_start" is zero.
// TODO: hwtest this
if (config.GetStartAddress() != 0) {
if (!is_second_filler) {
//Service::GSP::SignalInterrupt(Service::GSP::InterruptId::PSC0);
} else {
//Service::GSP::SignalInterrupt(Service::GSP::InterruptId::PSC1);
}
}
// Reset "trigger" flag and set the "finish" flag
// NOTE: This was confirmed to happen on hardware even if "address_start" is zero.
config.trigger.Assign(0);
config.finished.Assign(1);
}
break;
}
case GPU_REG_INDEX(display_transfer_config.trigger): {
MICROPROFILE_SCOPE(GPU_DisplayTransfer);
const auto& config = g_regs.display_transfer_config;
if (config.trigger & 1) {
if (Pica::g_debug_context)
Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::IncomingDisplayTransfer,
nullptr);
if (config.is_texture_copy) {
TextureCopy(config);
LOG_TRACE(HW_GPU, "TextureCopy: 0x%X bytes from 0x%08X(%u+%u)-> "
"0x%08X(%u+%u), flags 0x%08X",
config.texture_copy.size, config.GetPhysicalInputAddress(),
config.texture_copy.input_width * 16, config.texture_copy.input_gap * 16,
config.GetPhysicalOutputAddress(), config.texture_copy.output_width * 16,
config.texture_copy.output_gap * 16, config.flags);
} else {
DisplayTransfer(config);
LOG_TRACE(HW_GPU, "DisplayTransfer: 0x%08x(%ux%u)-> "
"0x%08x(%ux%u), dst format %x, flags 0x%08X",
config.GetPhysicalInputAddress(), config.input_width.Value(),
config.input_height.Value(), config.GetPhysicalOutputAddress(),
config.output_width.Value(), config.output_height.Value(),
config.output_format.Value(), config.flags);
}
g_regs.display_transfer_config.trigger = 0;
//Service::GSP::SignalInterrupt(Service::GSP::InterruptId::PPF);
}
break;
}
// Seems like writing to this register triggers processing
case GPU_REG_INDEX(command_processor_config.trigger): {
const auto& config = g_regs.command_processor_config;
if (config.trigger & 1) {
MICROPROFILE_SCOPE(GPU_CmdlistProcessing);
u32* buffer = (u32*)Memory::GetPhysicalPointer(config.GetPhysicalAddress());
if (Pica::g_debug_context && Pica::g_debug_context->recorder) {
Pica::g_debug_context->recorder->MemoryAccessed((u8*)buffer, config.size,
config.GetPhysicalAddress());
}
Pica::CommandProcessor::ProcessCommandList(buffer, config.size);
g_regs.command_processor_config.trigger = 0;
}
break;
}
default:
break;
}
// Notify tracer about the register write
// This is happening *after* handling the write to make sure we properly catch all memory reads.
if (Pica::g_debug_context && Pica::g_debug_context->recorder) {
// addr + GPU VBase - IO VBase + IO PBase
Pica::g_debug_context->recorder->RegisterWritten<T>(
addr + 0x1EF00000 - 0x1EC00000 + 0x10100000, data);
}
}
// Explicitly instantiate template functions because we aren't defining this in the header:
template void Read<u64>(u64& var, const u32 addr);
template void Read<u32>(u32& var, const u32 addr);
template void Read<u16>(u16& var, const u32 addr);
template void Read<u8>(u8& var, const u32 addr);
template void Write<u64>(u32 addr, const u64 data);
template void Write<u32>(u32 addr, const u32 data);
template void Write<u16>(u32 addr, const u16 data);
template void Write<u8>(u32 addr, const u8 data);
/// Update hardware
static void VBlankCallback(u64 userdata, int cycles_late) {
//VideoCore::g_renderer->SwapBuffers();
//// Signal to GSP that GPU interrupt has occurred
//// TODO(yuriks): hwtest to determine if PDC0 is for the Top screen and PDC1 for the Sub
//// screen, or if both use the same interrupts and these two instead determine the
//// beginning and end of the VBlank period. If needed, split the interrupt firing into
//// two different intervals.
//Service::GSP::SignalInterrupt(Service::GSP::InterruptId::PDC0);
//Service::GSP::SignalInterrupt(Service::GSP::InterruptId::PDC1);
// Reschedule recurrent event
CoreTiming::ScheduleEvent(frame_ticks - cycles_late, vblank_event);
}
/// Initialize hardware
void Init() {
memset(&g_regs, 0, sizeof(g_regs));
auto& framebuffer_top = g_regs.framebuffer_config[0];
auto& framebuffer_sub = g_regs.framebuffer_config[1];
// Setup default framebuffer addresses (located in VRAM)
// .. or at least these are the ones used by system applets.
// There's probably a smarter way to come up with addresses
// like this which does not require hardcoding.
framebuffer_top.address_left1 = 0x181E6000;
framebuffer_top.address_left2 = 0x1822C800;
framebuffer_top.address_right1 = 0x18273000;
framebuffer_top.address_right2 = 0x182B9800;
framebuffer_sub.address_left1 = 0x1848F000;
framebuffer_sub.address_left2 = 0x184C7800;
framebuffer_top.width.Assign(240);
framebuffer_top.height.Assign(400);
framebuffer_top.stride = 3 * 240;
framebuffer_top.color_format.Assign(Regs::PixelFormat::RGB8);
framebuffer_top.active_fb = 0;
framebuffer_sub.width.Assign(240);
framebuffer_sub.height.Assign(320);
framebuffer_sub.stride = 3 * 240;
framebuffer_sub.color_format.Assign(Regs::PixelFormat::RGB8);
framebuffer_sub.active_fb = 0;
vblank_event = CoreTiming::RegisterEvent("GPU::VBlankCallback", VBlankCallback);
CoreTiming::ScheduleEvent(frame_ticks, vblank_event);
LOG_DEBUG(HW_GPU, "initialized OK");
}
/// Shutdown hardware
void Shutdown() {
LOG_DEBUG(HW_GPU, "shutdown OK");
}
} // namespace

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src/core/hw/gpu.h
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@ -1,334 +0,0 @@
// Copyright 2014 Citra Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#pragma once
#include <cstddef>
#include <type_traits>
#include "common/assert.h"
#include "common/bit_field.h"
#include "common/common_funcs.h"
#include "common/common_types.h"
namespace GPU {
constexpr float SCREEN_REFRESH_RATE = 60;
// Returns index corresponding to the Regs member labeled by field_name
// TODO: Due to Visual studio bug 209229, offsetof does not return constant expressions
// when used with array elements (e.g. GPU_REG_INDEX(memory_fill_config[0])).
// For details cf.
// https://connect.microsoft.com/VisualStudio/feedback/details/209229/offsetof-does-not-produce-a-constant-expression-for-array-members
// Hopefully, this will be fixed sometime in the future.
// For lack of better alternatives, we currently hardcode the offsets when constant
// expressions are needed via GPU_REG_INDEX_WORKAROUND (on sane compilers, static_asserts
// will then make sure the offsets indeed match the automatically calculated ones).
#define GPU_REG_INDEX(field_name) (offsetof(GPU::Regs, field_name) / sizeof(u32))
#if defined(_MSC_VER)
#define GPU_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) (backup_workaround_index)
#else
// NOTE: Yeah, hacking in a static_assert here just to workaround the lacking MSVC compiler
// really is this annoying. This macro just forwards its first argument to GPU_REG_INDEX
// and then performs a (no-op) cast to size_t iff the second argument matches the expected
// field offset. Otherwise, the compiler will fail to compile this code.
#define GPU_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) \
((typename std::enable_if<backup_workaround_index == GPU_REG_INDEX(field_name), size_t>::type) \
GPU_REG_INDEX(field_name))
#endif
// MMIO region 0x1EFxxxxx
struct Regs {
// helper macro to make sure the defined structures are of the expected size.
#if defined(_MSC_VER)
// TODO: MSVC does not support using sizeof() on non-static data members even though this
// is technically allowed since C++11. This macro should be enabled once MSVC adds
// support for that.
#define ASSERT_MEMBER_SIZE(name, size_in_bytes)
#else
#define ASSERT_MEMBER_SIZE(name, size_in_bytes) \
static_assert(sizeof(name) == size_in_bytes, \
"Structure size and register block length don't match")
#endif
// Components are laid out in reverse byte order, most significant bits first.
enum class PixelFormat : u32 {
RGBA8 = 0,
RGB8 = 1,
RGB565 = 2,
RGB5A1 = 3,
RGBA4 = 4,
};
/**
* Returns the number of bytes per pixel.
*/
static int BytesPerPixel(PixelFormat format) {
switch (format) {
case PixelFormat::RGBA8:
return 4;
case PixelFormat::RGB8:
return 3;
case PixelFormat::RGB565:
case PixelFormat::RGB5A1:
case PixelFormat::RGBA4:
return 2;
}
UNREACHABLE();
}
INSERT_PADDING_WORDS(0x4);
struct MemoryFillConfig {
u32 address_start;
u32 address_end;
union {
u32 value_32bit;
BitField<0, 16, u32> value_16bit;
// TODO: Verify component order
BitField<0, 8, u32> value_24bit_r;
BitField<8, 8, u32> value_24bit_g;
BitField<16, 8, u32> value_24bit_b;
};
union {
u32 control;
// Setting this field to 1 triggers the memory fill.
// This field also acts as a status flag, and gets reset to 0 upon completion.
BitField<0, 1, u32> trigger;
// Set to 1 upon completion.
BitField<1, 1, u32> finished;
// If both of these bits are unset, then it will fill the memory with a 16 bit value
// 1: fill with 24-bit wide values
BitField<8, 1, u32> fill_24bit;
// 1: fill with 32-bit wide values
BitField<9, 1, u32> fill_32bit;
};
inline u32 GetStartAddress() const {
return DecodeAddressRegister(address_start);
}
inline u32 GetEndAddress() const {
return DecodeAddressRegister(address_end);
}
} memory_fill_config[2];
ASSERT_MEMBER_SIZE(memory_fill_config[0], 0x10);
INSERT_PADDING_WORDS(0x10b);
struct FramebufferConfig {
union {
u32 size;
BitField<0, 16, u32> width;
BitField<16, 16, u32> height;
};
INSERT_PADDING_WORDS(0x2);
u32 address_left1;
u32 address_left2;
union {
u32 format;
BitField<0, 3, PixelFormat> color_format;
};
INSERT_PADDING_WORDS(0x1);
union {
u32 active_fb;
// 0: Use parameters ending with "1"
// 1: Use parameters ending with "2"
BitField<0, 1, u32> second_fb_active;
};
INSERT_PADDING_WORDS(0x5);
// Distance between two pixel rows, in bytes
u32 stride;
u32 address_right1;
u32 address_right2;
INSERT_PADDING_WORDS(0x30);
} framebuffer_config[2];
ASSERT_MEMBER_SIZE(framebuffer_config[0], 0x100);
INSERT_PADDING_WORDS(0x169);
struct DisplayTransferConfig {
u32 input_address;
u32 output_address;
inline u32 GetPhysicalInputAddress() const {
return DecodeAddressRegister(input_address);
}
inline u32 GetPhysicalOutputAddress() const {
return DecodeAddressRegister(output_address);
}
union {
u32 output_size;
BitField<0, 16, u32> output_width;
BitField<16, 16, u32> output_height;
};
union {
u32 input_size;
BitField<0, 16, u32> input_width;
BitField<16, 16, u32> input_height;
};
enum ScalingMode : u32 {
NoScale = 0, // Doesn't scale the image
ScaleX = 1, // Downscales the image in half in the X axis and applies a box filter
ScaleXY =
2, // Downscales the image in half in both the X and Y axes and applies a box filter
};
union {
u32 flags;
BitField<0, 1, u32> flip_vertically; // flips input data vertically
BitField<1, 1, u32> input_linear; // Converts from linear to tiled format
BitField<2, 1, u32> crop_input_lines;
BitField<3, 1, u32> is_texture_copy; // Copies the data without performing any
// processing and respecting texture copy fields
BitField<5, 1, u32> dont_swizzle;
BitField<8, 3, PixelFormat> input_format;
BitField<12, 3, PixelFormat> output_format;
/// Uses some kind of 32x32 block swizzling mode, instead of the usual 8x8 one.
BitField<16, 1, u32> block_32; // TODO(yuriks): unimplemented
BitField<24, 2, ScalingMode> scaling; // Determines the scaling mode of the transfer
};
INSERT_PADDING_WORDS(0x1);
// it seems that writing to this field triggers the display transfer
u32 trigger;
INSERT_PADDING_WORDS(0x1);
struct {
u32 size; // The lower 4 bits are ignored
union {
u32 input_size;
BitField<0, 16, u32> input_width;
BitField<16, 16, u32> input_gap;
};
union {
u32 output_size;
BitField<0, 16, u32> output_width;
BitField<16, 16, u32> output_gap;
};
} texture_copy;
} display_transfer_config;
ASSERT_MEMBER_SIZE(display_transfer_config, 0x2c);
INSERT_PADDING_WORDS(0x32D);
struct {
// command list size (in bytes)
u32 size;
INSERT_PADDING_WORDS(0x1);
// command list address
u32 address;
INSERT_PADDING_WORDS(0x1);
// it seems that writing to this field triggers command list processing
u32 trigger;
inline u32 GetPhysicalAddress() const {
return DecodeAddressRegister(address);
}
} command_processor_config;
ASSERT_MEMBER_SIZE(command_processor_config, 0x14);
INSERT_PADDING_WORDS(0x9c3);
static constexpr size_t NumIds() {
return sizeof(Regs) / sizeof(u32);
}
const u32& operator[](int index) const {
const u32* content = reinterpret_cast<const u32*>(this);
return content[index];
}
u32& operator[](int index) {
u32* content = reinterpret_cast<u32*>(this);
return content[index];
}
#undef ASSERT_MEMBER_SIZE
private:
/*
* Most physical addresses which GPU registers refer to are 8-byte aligned.
* This function should be used to get the address from a raw register value.
*/
static inline u32 DecodeAddressRegister(u32 register_value) {
return register_value * 8;
}
};
static_assert(std::is_standard_layout<Regs>::value, "Structure does not use standard layout");
// TODO: MSVC does not support using offsetof() on non-static data members even though this
// is technically allowed since C++11. This macro should be enabled once MSVC adds
// support for that.
#ifndef _MSC_VER
#define ASSERT_REG_POSITION(field_name, position) \
static_assert(offsetof(Regs, field_name) == position * 4, \
"Field " #field_name " has invalid position")
ASSERT_REG_POSITION(memory_fill_config[0], 0x00004);
ASSERT_REG_POSITION(memory_fill_config[1], 0x00008);
ASSERT_REG_POSITION(framebuffer_config[0], 0x00117);
ASSERT_REG_POSITION(framebuffer_config[1], 0x00157);
ASSERT_REG_POSITION(display_transfer_config, 0x00300);
ASSERT_REG_POSITION(command_processor_config, 0x00638);
#undef ASSERT_REG_POSITION
#endif // !defined(_MSC_VER)
// The total number of registers is chosen arbitrarily, but let's make sure it's not some odd value
// anyway.
static_assert(sizeof(Regs) == 0x1000 * sizeof(u32), "Invalid total size of register set");
extern Regs g_regs;
template <typename T>
void Read(T& var, const u32 addr);
template <typename T>
void Write(u32 addr, const T data);
/// Initialize hardware
void Init();
/// Shutdown hardware
void Shutdown();
} // namespace