shader: Partial implementation of LDC
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parent
ab46371247
commit
3a63fa0477
16 changed files with 405 additions and 50 deletions
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@ -112,7 +112,27 @@ void IREmitter::SetPred(IR::Pred pred, const U1& value) {
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}
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U32 IREmitter::GetCbuf(const U32& binding, const U32& byte_offset) {
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return Inst<U32>(Opcode::GetCbuf, binding, byte_offset);
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return Inst<U32>(Opcode::GetCbufU32, binding, byte_offset);
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}
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UAny IREmitter::GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
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bool is_signed) {
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switch (bitsize) {
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case 8:
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return Inst<U32>(is_signed ? Opcode::GetCbufS8 : Opcode::GetCbufU8, binding, byte_offset);
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case 16:
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return Inst<U32>(is_signed ? Opcode::GetCbufS16 : Opcode::GetCbufU16, binding, byte_offset);
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case 32:
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return Inst<U32>(Opcode::GetCbufU32, binding, byte_offset);
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case 64:
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return Inst<U64>(Opcode::GetCbufU64, binding, byte_offset);
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default:
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throw InvalidArgument("Invalid bit size {}", bitsize);
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}
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}
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F32 IREmitter::GetFloatCbuf(const U32& binding, const U32& byte_offset) {
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return Inst<F32>(Opcode::GetCbufF32, binding, byte_offset);
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}
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U1 IREmitter::GetZFlag() {
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@ -47,6 +47,9 @@ public:
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void SetGotoVariable(u32 id, const U1& value);
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[[nodiscard]] U32 GetCbuf(const U32& binding, const U32& byte_offset);
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[[nodiscard]] UAny GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
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bool is_signed);
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[[nodiscard]] F32 GetFloatCbuf(const U32& binding, const U32& byte_offset);
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[[nodiscard]] U1 GetZFlag();
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[[nodiscard]] U1 GetSFlag();
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@ -21,7 +21,13 @@ OPCODE(GetPred, U1, Pred
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OPCODE(SetPred, Void, Pred, U1, )
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OPCODE(GetGotoVariable, U1, U32, )
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OPCODE(SetGotoVariable, Void, U32, U1, )
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OPCODE(GetCbuf, U32, U32, U32, )
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OPCODE(GetCbufU8, U32, U32, U32, )
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OPCODE(GetCbufS8, U32, U32, U32, )
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OPCODE(GetCbufU16, U32, U32, U32, )
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OPCODE(GetCbufS16, U32, U32, U32, )
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OPCODE(GetCbufU32, U32, U32, U32, )
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OPCODE(GetCbufF32, F32, U32, U32, )
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OPCODE(GetCbufU64, U64, U32, U32, )
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OPCODE(GetAttribute, U32, Attribute, )
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OPCODE(SetAttribute, Void, Attribute, U32, )
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OPCODE(GetAttributeIndexed, U32, U32, )
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@ -56,25 +56,32 @@ IR::F32 TranslatorVisitor::GetFloatReg39(u64 insn) {
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return ir.BitCast<IR::F32>(GetReg39(insn));
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}
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IR::U32 TranslatorVisitor::GetCbuf(u64 insn) {
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static std::pair<IR::U32, IR::U32> CbufAddr(u64 insn) {
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union {
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u64 raw;
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BitField<20, 14, s64> offset;
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BitField<34, 5, u64> binding;
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} const cbuf{insn};
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if (cbuf.binding >= 18) {
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throw NotImplementedException("Out of bounds constant buffer binding {}", cbuf.binding);
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}
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if (cbuf.offset >= 0x10'000 || cbuf.offset < 0) {
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throw NotImplementedException("Out of bounds constant buffer offset {}", cbuf.offset);
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}
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const IR::U32 binding{ir.Imm32(static_cast<u32>(cbuf.binding))};
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const IR::U32 byte_offset{ir.Imm32(static_cast<u32>(cbuf.offset) * 4)};
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const IR::Value binding{static_cast<u32>(cbuf.binding)};
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const IR::Value byte_offset{static_cast<u32>(cbuf.offset) * 4};
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return {IR::U32{binding}, IR::U32{byte_offset}};
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}
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IR::U32 TranslatorVisitor::GetCbuf(u64 insn) {
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const auto[binding, byte_offset]{CbufAddr(insn)};
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return ir.GetCbuf(binding, byte_offset);
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}
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IR::F32 TranslatorVisitor::GetFloatCbuf(u64 insn) {
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return ir.BitCast<IR::F32>(GetCbuf(insn));
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const auto[binding, byte_offset]{CbufAddr(insn)};
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return ir.GetFloatCbuf(binding, byte_offset);
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}
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IR::U32 TranslatorVisitor::GetImm20(u64 insn) {
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@ -83,6 +90,7 @@ IR::U32 TranslatorVisitor::GetImm20(u64 insn) {
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BitField<20, 19, u64> value;
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BitField<56, 1, u64> is_negative;
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} const imm{insn};
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if (imm.is_negative != 0) {
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const s64 raw{static_cast<s64>(imm.value)};
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return ir.Imm32(static_cast<s32>(-(1LL << 19) + raw));
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@ -0,0 +1,85 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class Mode : u64 {
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Default,
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IL,
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IS,
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ISL,
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};
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enum class Size : u64 {
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U8,
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S8,
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U16,
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S16,
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B32,
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B64,
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};
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std::pair<IR::U32, IR::U32> Slot(IR::IREmitter& ir, Mode mode, const IR::U32& imm_index,
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const IR::U32& reg, const IR::U32& imm) {
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switch (mode) {
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case Mode::Default:
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return {imm_index, ir.IAdd(reg, imm)};
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default:
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break;
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}
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throw NotImplementedException("Mode {}", mode);
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}
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} // Anonymous namespace
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void TranslatorVisitor::LDC(u64 insn) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_reg;
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BitField<20, 16, s64> offset;
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BitField<36, 5, u64> index;
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BitField<44, 2, Mode> mode;
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BitField<48, 3, Size> size;
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} const ldc{insn};
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const IR::U32 imm_index{ir.Imm32(static_cast<u32>(ldc.index))};
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const IR::U32 reg{X(ldc.src_reg)};
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const IR::U32 imm{ir.Imm32(static_cast<s32>(ldc.offset))};
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const auto [index, offset]{Slot(ir, ldc.mode, imm_index, reg, imm)};
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switch (ldc.size) {
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case Size::U8:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 8, false));
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break;
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case Size::S8:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 8, true));
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break;
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case Size::U16:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 16, false));
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break;
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case Size::S16:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 16, true));
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break;
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case Size::B32:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 32, false));
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break;
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case Size::B64: {
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if (!IR::IsAligned(ldc.dest_reg, 2)) {
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throw NotImplementedException("Unaligned destination register");
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}
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const IR::Value vector{ir.UnpackUint2x32(ir.GetCbuf(index, offset, 64, false))};
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for (int i = 0; i < 2; ++i) {
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X(ldc.dest_reg + i, IR::U32{ir.CompositeExtract(vector, i)});
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}
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break;
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}
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default:
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throw NotImplementedException("Invalid size {}", ldc.size.Value());
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}
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}
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} // namespace Shader::Maxwell
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@ -425,10 +425,6 @@ void TranslatorVisitor::LD(u64) {
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ThrowNotImplemented(Opcode::LD);
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}
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void TranslatorVisitor::LDC(u64) {
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ThrowNotImplemented(Opcode::LDC);
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}
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void TranslatorVisitor::LDL(u64) {
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ThrowNotImplemented(Opcode::LDL);
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}
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