shader: Partial implementation of LDC

This commit is contained in:
ReinUsesLisp 2021-03-09 17:14:57 -03:00 committed by ameerj
parent ab46371247
commit 3a63fa0477
16 changed files with 405 additions and 50 deletions

View file

@ -112,7 +112,27 @@ void IREmitter::SetPred(IR::Pred pred, const U1& value) {
}
U32 IREmitter::GetCbuf(const U32& binding, const U32& byte_offset) {
return Inst<U32>(Opcode::GetCbuf, binding, byte_offset);
return Inst<U32>(Opcode::GetCbufU32, binding, byte_offset);
}
UAny IREmitter::GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
bool is_signed) {
switch (bitsize) {
case 8:
return Inst<U32>(is_signed ? Opcode::GetCbufS8 : Opcode::GetCbufU8, binding, byte_offset);
case 16:
return Inst<U32>(is_signed ? Opcode::GetCbufS16 : Opcode::GetCbufU16, binding, byte_offset);
case 32:
return Inst<U32>(Opcode::GetCbufU32, binding, byte_offset);
case 64:
return Inst<U64>(Opcode::GetCbufU64, binding, byte_offset);
default:
throw InvalidArgument("Invalid bit size {}", bitsize);
}
}
F32 IREmitter::GetFloatCbuf(const U32& binding, const U32& byte_offset) {
return Inst<F32>(Opcode::GetCbufF32, binding, byte_offset);
}
U1 IREmitter::GetZFlag() {

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@ -47,6 +47,9 @@ public:
void SetGotoVariable(u32 id, const U1& value);
[[nodiscard]] U32 GetCbuf(const U32& binding, const U32& byte_offset);
[[nodiscard]] UAny GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
bool is_signed);
[[nodiscard]] F32 GetFloatCbuf(const U32& binding, const U32& byte_offset);
[[nodiscard]] U1 GetZFlag();
[[nodiscard]] U1 GetSFlag();

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@ -21,7 +21,13 @@ OPCODE(GetPred, U1, Pred
OPCODE(SetPred, Void, Pred, U1, )
OPCODE(GetGotoVariable, U1, U32, )
OPCODE(SetGotoVariable, Void, U32, U1, )
OPCODE(GetCbuf, U32, U32, U32, )
OPCODE(GetCbufU8, U32, U32, U32, )
OPCODE(GetCbufS8, U32, U32, U32, )
OPCODE(GetCbufU16, U32, U32, U32, )
OPCODE(GetCbufS16, U32, U32, U32, )
OPCODE(GetCbufU32, U32, U32, U32, )
OPCODE(GetCbufF32, F32, U32, U32, )
OPCODE(GetCbufU64, U64, U32, U32, )
OPCODE(GetAttribute, U32, Attribute, )
OPCODE(SetAttribute, Void, Attribute, U32, )
OPCODE(GetAttributeIndexed, U32, U32, )

View file

@ -56,25 +56,32 @@ IR::F32 TranslatorVisitor::GetFloatReg39(u64 insn) {
return ir.BitCast<IR::F32>(GetReg39(insn));
}
IR::U32 TranslatorVisitor::GetCbuf(u64 insn) {
static std::pair<IR::U32, IR::U32> CbufAddr(u64 insn) {
union {
u64 raw;
BitField<20, 14, s64> offset;
BitField<34, 5, u64> binding;
} const cbuf{insn};
if (cbuf.binding >= 18) {
throw NotImplementedException("Out of bounds constant buffer binding {}", cbuf.binding);
}
if (cbuf.offset >= 0x10'000 || cbuf.offset < 0) {
throw NotImplementedException("Out of bounds constant buffer offset {}", cbuf.offset);
}
const IR::U32 binding{ir.Imm32(static_cast<u32>(cbuf.binding))};
const IR::U32 byte_offset{ir.Imm32(static_cast<u32>(cbuf.offset) * 4)};
const IR::Value binding{static_cast<u32>(cbuf.binding)};
const IR::Value byte_offset{static_cast<u32>(cbuf.offset) * 4};
return {IR::U32{binding}, IR::U32{byte_offset}};
}
IR::U32 TranslatorVisitor::GetCbuf(u64 insn) {
const auto[binding, byte_offset]{CbufAddr(insn)};
return ir.GetCbuf(binding, byte_offset);
}
IR::F32 TranslatorVisitor::GetFloatCbuf(u64 insn) {
return ir.BitCast<IR::F32>(GetCbuf(insn));
const auto[binding, byte_offset]{CbufAddr(insn)};
return ir.GetFloatCbuf(binding, byte_offset);
}
IR::U32 TranslatorVisitor::GetImm20(u64 insn) {
@ -83,6 +90,7 @@ IR::U32 TranslatorVisitor::GetImm20(u64 insn) {
BitField<20, 19, u64> value;
BitField<56, 1, u64> is_negative;
} const imm{insn};
if (imm.is_negative != 0) {
const s64 raw{static_cast<s64>(imm.value)};
return ir.Imm32(static_cast<s32>(-(1LL << 19) + raw));

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@ -0,0 +1,85 @@
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "common/bit_field.h"
#include "common/common_types.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
namespace Shader::Maxwell {
namespace {
enum class Mode : u64 {
Default,
IL,
IS,
ISL,
};
enum class Size : u64 {
U8,
S8,
U16,
S16,
B32,
B64,
};
std::pair<IR::U32, IR::U32> Slot(IR::IREmitter& ir, Mode mode, const IR::U32& imm_index,
const IR::U32& reg, const IR::U32& imm) {
switch (mode) {
case Mode::Default:
return {imm_index, ir.IAdd(reg, imm)};
default:
break;
}
throw NotImplementedException("Mode {}", mode);
}
} // Anonymous namespace
void TranslatorVisitor::LDC(u64 insn) {
union {
u64 raw;
BitField<0, 8, IR::Reg> dest_reg;
BitField<8, 8, IR::Reg> src_reg;
BitField<20, 16, s64> offset;
BitField<36, 5, u64> index;
BitField<44, 2, Mode> mode;
BitField<48, 3, Size> size;
} const ldc{insn};
const IR::U32 imm_index{ir.Imm32(static_cast<u32>(ldc.index))};
const IR::U32 reg{X(ldc.src_reg)};
const IR::U32 imm{ir.Imm32(static_cast<s32>(ldc.offset))};
const auto [index, offset]{Slot(ir, ldc.mode, imm_index, reg, imm)};
switch (ldc.size) {
case Size::U8:
X(ldc.dest_reg, ir.GetCbuf(index, offset, 8, false));
break;
case Size::S8:
X(ldc.dest_reg, ir.GetCbuf(index, offset, 8, true));
break;
case Size::U16:
X(ldc.dest_reg, ir.GetCbuf(index, offset, 16, false));
break;
case Size::S16:
X(ldc.dest_reg, ir.GetCbuf(index, offset, 16, true));
break;
case Size::B32:
X(ldc.dest_reg, ir.GetCbuf(index, offset, 32, false));
break;
case Size::B64: {
if (!IR::IsAligned(ldc.dest_reg, 2)) {
throw NotImplementedException("Unaligned destination register");
}
const IR::Value vector{ir.UnpackUint2x32(ir.GetCbuf(index, offset, 64, false))};
for (int i = 0; i < 2; ++i) {
X(ldc.dest_reg + i, IR::U32{ir.CompositeExtract(vector, i)});
}
break;
}
default:
throw NotImplementedException("Invalid size {}", ldc.size.Value());
}
}
} // namespace Shader::Maxwell

View file

@ -425,10 +425,6 @@ void TranslatorVisitor::LD(u64) {
ThrowNotImplemented(Opcode::LD);
}
void TranslatorVisitor::LDC(u64) {
ThrowNotImplemented(Opcode::LDC);
}
void TranslatorVisitor::LDL(u64) {
ThrowNotImplemented(Opcode::LDL);
}