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shader: Implement SR_LaneId

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This commit is contained in:
FernandoS27 2021-04-02 23:05:47 +02:00 • committed by ameerj
parent 595806fb1c
commit 45d547af11
7 changed files with 15 additions and 0 deletions
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4
src/shader_recompiler/frontend/ir/ir_emitter.cpp
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@ -355,6 +355,10 @@ U32 IREmitter::LocalInvocationIdZ() {
return U32{CompositeExtract(Inst(Opcode::LocalInvocationId), 2)};
}
U32 IREmitter::LaneId() {
return Inst<U32>(Opcode::LaneId);
}
U32 IREmitter::LoadGlobalU8(const U64& address) {
return Inst<U32>(Opcode::LoadGlobalU8, address);
}

2
src/shader_recompiler/frontend/ir/ir_emitter.h
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@ -97,6 +97,8 @@ public:
[[nodiscard]] U32 LocalInvocationIdY();
[[nodiscard]] U32 LocalInvocationIdZ();
[[nodiscard]] U32 LaneId();
[[nodiscard]] U32 LoadGlobalU8(const U64& address);
[[nodiscard]] U32 LoadGlobalS8(const U64& address);
[[nodiscard]] U32 LoadGlobalU16(const U64& address);

1
src/shader_recompiler/frontend/ir/opcodes.inc
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@ -63,6 +63,7 @@ OPCODE(SetTRFlag, Void, U1,
OPCODE(SetMXFlag, Void, U1, )
OPCODE(WorkgroupId, U32x3, )
OPCODE(LocalInvocationId, U32x3, )
OPCODE(LaneId, U32, )
// Undefined
OPCODE(UndefU1, U1, )

2
src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp
View file

@ -99,6 +99,8 @@ enum class SpecialRegister : u64 {
return ir.Imm32(Common::BitCast<u32>(1.0f));
case SpecialRegister::SR_WSCALEFACTOR_Z:
return ir.Imm32(Common::BitCast<u32>(1.0f));
case SpecialRegister::SR_LANEID:
return ir.LaneId();
default:
throw NotImplementedException("S2R special register {}", special_register);
}