dyncom: Move CP15 register reading into its own function.
Keeps everything contained. Added all supported readable registers in an ARM11 MPCore.
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Lioncash
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4 changed files with 253 additions and 49 deletions
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@ -15,7 +15,9 @@
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "core/mem_map.h"
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/arm_regformat.h"
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// Unsigned sum of absolute difference
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u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right)
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@ -213,3 +215,197 @@ bool InAPrivilegedMode(ARMul_State* cpu)
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{
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return (cpu->Mode != USER32MODE);
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}
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// Reads from the CP15 registers. Used with implementation of the MRC instruction.
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// Note that since the 3DS does not have the hypervisor extensions, these registers
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// are not implemented.
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u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
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{
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// Unprivileged registers
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if (crn == 13 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_THREAD_UPRW)];
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// TODO: Whenever TLS is implemented, this should return
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// "cpu->CP15[CP15(CP15_THREAD_URO)];"
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// which contains the address of the 0x200-byte TLS
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if (opcode_2 == 3)
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return Memory::KERNEL_MEMORY_VADDR;
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}
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if (InAPrivilegedMode(cpu))
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{
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if (crn == 0 && opcode_1 == 0)
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{
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if (crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_MAIN_ID)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_CACHE_TYPE)];
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if (opcode_2 == 3)
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return cpu->CP15[CP15(CP15_TLB_TYPE)];
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if (opcode_2 == 5)
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return cpu->CP15[CP15(CP15_CPU_ID)];
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}
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else if (crm == 1)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_0)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_1)];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_DEBUG_FEATURE_0)];
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if (opcode_2 == 4)
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return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_0)];
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if (opcode_2 == 5)
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return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_1)];
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if (opcode_2 == 6)
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return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_2)];
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if (opcode_2 == 7)
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return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_3)];
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}
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else if (crm == 2)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_0)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_1)];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_2)];
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if (opcode_2 == 3)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_3)];
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if (opcode_2 == 4)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_4)];
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}
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}
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if (crn == 1 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_CONTROL)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)];
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}
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if (crn == 2 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)];
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}
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if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)];
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if (crn == 5 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_FAULT_STATUS)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)];
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}
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if (crn == 6 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_FAULT_ADDRESS)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_WFAR)];
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}
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if (crn == 7 && opcode_1 == 0 && crm == 4 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PHYS_ADDRESS)];
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if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_DATA_CACHE_LOCKDOWN)];
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if (crn == 10 && opcode_1 == 0)
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{
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if (crm == 0 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_TLB_LOCKDOWN)];
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if (crm == 2)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PRIMARY_REGION_REMAP)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_NORMAL_REGION_REMAP)];
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}
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}
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if (crn == 13 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PID)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_CONTEXT_ID)];
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if (opcode_2 == 4)
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return cpu->CP15[CP15(CP15_THREAD_PRW)];
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}
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if (crn == 15)
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{
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if (opcode_1 == 0 && crm == 12)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PERFORMANCE_MONITOR_CONTROL)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_CYCLE_COUNTER)];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_COUNT_0)];
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if (opcode_2 == 3)
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return cpu->CP15[CP15(CP15_COUNT_1)];
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}
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if (opcode_1 == 5 && opcode_2 == 2)
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{
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if (crm == 5)
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return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS)];
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if (crm == 6)
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return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS)];
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if (crm == 7)
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return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE)];
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}
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if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_TLB_DEBUG_CONTROL)];
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}
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}
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LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2);
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return 0;
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}
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