dyncom: Move CP15 register reading into its own function.

Keeps everything contained. Added all supported readable registers in an ARM11 MPCore.

src/core/arm/skyeye_common/arm_regformat.h

@@ -50,6 +50,8 @@ enum {
     EXCLUSIVE_TAG,
     EXCLUSIVE_STATE,
     EXCLUSIVE_RESULT,
+
+    // c0 - Information registers
     CP15_BASE,
     CP15_C0 = CP15_BASE,
     CP15_C0_C0 = CP15_C0,
@@ -57,15 +59,30 @@ enum {
     CP15_CACHE_TYPE,
     CP15_TCM_STATUS,
     CP15_TLB_TYPE,
+    CP15_CPU_ID,
     CP15_C0_C1,
     CP15_PROCESSOR_FEATURE_0 = CP15_C0_C1,
     CP15_PROCESSOR_FEATURE_1,
     CP15_DEBUG_FEATURE_0,
     CP15_AUXILIARY_FEATURE_0,
+    CP15_MEMORY_MODEL_FEATURE_0,
+    CP15_MEMORY_MODEL_FEATURE_1,
+    CP15_MEMORY_MODEL_FEATURE_2,
+    CP15_MEMORY_MODEL_FEATURE_3,
+    CP15_C0_C2,
+    CP15_ISA_FEATURE_0 = CP15_C0_C2,
+    CP15_ISA_FEATURE_1,
+    CP15_ISA_FEATURE_2,
+    CP15_ISA_FEATURE_3,
+    CP15_ISA_FEATURE_4,
+
+    // c1 - Control registers
     CP15_C1_C0,
     CP15_CONTROL = CP15_C1_C0,
     CP15_AUXILIARY_CONTROL,
     CP15_COPROCESSOR_ACCESS_CONTROL,
+
+    // c2 - Translation table registers
     CP15_C2,
     CP15_C2_C0 = CP15_C2,
     CP15_TRANSLATION_BASE = CP15_C2_C0,
@@ -74,24 +91,54 @@ enum {
     CP15_TRANSLATION_BASE_CONTROL,
     CP15_DOMAIN_ACCESS_CONTROL,
     CP15_RESERVED,
-    /* Fault status */
+
+    // c5 - Fault status registers
     CP15_FAULT_STATUS,
     CP15_INSTR_FAULT_STATUS,
     CP15_COMBINED_DATA_FSR = CP15_FAULT_STATUS,
     CP15_INST_FSR,
-    /* Fault Address register */
+
+    // c6 - Fault Address registers
     CP15_FAULT_ADDRESS,
     CP15_COMBINED_DATA_FAR = CP15_FAULT_ADDRESS,
     CP15_WFAR,
     CP15_IFAR,
+
+    // c7 - Cache operation registers
+    CP15_PHYS_ADDRESS,
+
+    // c9 - Data cache lockdown register
+    CP15_DATA_CACHE_LOCKDOWN,
+
+    // c10 - TLB/Memory map registers
+    CP15_TLB_LOCKDOWN,
+    CP15_PRIMARY_REGION_REMAP,
+    CP15_NORMAL_REGION_REMAP,
+
+    // c13 - Thread related registers
     CP15_PID,
     CP15_CONTEXT_ID,
     CP15_THREAD_UPRW, // Thread ID register - User/Privileged Read/Write
     CP15_THREAD_URO,  // Thread ID register - User Read Only (Privileged R/W)
     CP15_THREAD_PRW,  // Thread ID register - Privileged R/W only.
-    CP15_TLB_FAULT_ADDR, /* defined by SkyEye */
-    CP15_TLB_FAULT_STATUS, /* defined by SkyEye */
-    /* VFP registers */
+
+    // c15 - Performance and TLB lockdown registers
+    CP15_PERFORMANCE_MONITOR_CONTROL,
+    CP15_CYCLE_COUNTER,
+    CP15_COUNT_0,
+    CP15_COUNT_1,
+    CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY,
+    CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY,
+    CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS,
+    CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS,
+    CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE,
+    CP15_TLB_DEBUG_CONTROL,
+
+    // Skyeye defined
+    CP15_TLB_FAULT_ADDR,
+    CP15_TLB_FAULT_STATUS,
+
+    // VFP registers
     VFP_BASE,
     VFP_FPSID = VFP_BASE,
     VFP_FPSCR,

src/core/arm/skyeye_common/armdefs.h

@@ -358,3 +358,5 @@ extern u32 ARMul_UnsignedSatQ(s32, u8, bool*);
 
 extern bool InBigEndianMode(ARMul_State*);
 extern bool InAPrivilegedMode(ARMul_State*);
+
+extern u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);