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shader: Implement FSWZADD

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This commit is contained in:
ameerj 2021-03-28 22:23:45 -04:00
parent 34aba9627a
commit 6c51f49632
14 changed files with 87 additions and 4 deletions
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3
src/shader_recompiler/frontend/ir/ir_emitter.cpp
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@ -1602,4 +1602,7 @@ U32 IREmitter::ShuffleButterfly(const IR::U32& value, const IR::U32& index, cons
const IR::U32& seg_mask) {
return Inst<U32>(Opcode::ShuffleButterfly, value, index, clamp, seg_mask);
}
F32 IREmitter::FSwizzleAdd(const F32& a, const F32& b, const U32& swizzle, FpControl control) {
return Inst<F32>(Opcode::FSwizzleAdd, Flags{control}, a, b, swizzle);
}
} // namespace Shader::IR

2
src/shader_recompiler/frontend/ir/ir_emitter.h
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@ -277,6 +277,8 @@ public:
const IR::U32& seg_mask);
[[nodiscard]] U32 ShuffleButterfly(const IR::U32& value, const IR::U32& index,
const IR::U32& clamp, const IR::U32& seg_mask);
[[nodiscard]] F32 FSwizzleAdd(const F32& a, const F32& b, const U32& swizzle,
FpControl control = {});
private:
IR::Block::iterator insertion_point;

1
src/shader_recompiler/frontend/ir/opcodes.inc
View file

@ -408,3 +408,4 @@ OPCODE(ShuffleIndex, U32, U32,
OPCODE(ShuffleUp, U32, U32, U32, U32, U32, )
OPCODE(ShuffleDown, U32, U32, U32, U32, U32, )
OPCODE(ShuffleButterfly, U32, U32, U32, U32, U32, )
OPCODE(FSwizzleAdd, F32, F32, F32, U32, )

44
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp Normal file
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@ -0,0 +1,44 @@
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "common/common_types.h"
#include "shader_recompiler/exception.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/common_encoding.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
namespace Shader::Maxwell {
void TranslatorVisitor::FSWZADD(u64 insn) {
union {
u64 raw;
BitField<0, 8, IR::Reg> dest_reg;
BitField<28, 8, u64> swizzle;
BitField<38, 1, u64> ndv;
BitField<39, 2, FpRounding> round;
BitField<44, 1, u64> ftz;
BitField<47, 1, u64> cc;
} const fswzadd{insn};
if (fswzadd.ndv != 0) {
throw NotImplementedException("FSWZADD NDV");
}
const IR::F32 src_a{GetFloatReg8(insn)};
const IR::F32 src_b{GetFloatReg20(insn)};
const IR::U32 swizzle{ir.Imm32(static_cast<u32>(fswzadd.swizzle))};
const IR::FpControl fp_control{
.no_contraction{false},
.rounding{CastFpRounding(fswzadd.round)},
.fmz_mode{fswzadd.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None},
};
const IR::F32 result{ir.FSwizzleAdd(src_a, src_b, swizzle, fp_control)};
F(fswzadd.dest_reg, result);
if (fswzadd.cc != 0) {
throw NotImplementedException("FSWZADD CC");
}
}
} // namespace Shader::Maxwell

4
src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
View file

@ -91,6 +91,10 @@ IR::U32 TranslatorVisitor::GetReg39(u64 insn) {
return X(reg.index);
}
IR::F32 TranslatorVisitor::GetFloatReg8(u64 insn) {
return ir.BitCast<IR::F32>(GetReg8(insn));
}
IR::F32 TranslatorVisitor::GetFloatReg20(u64 insn) {
return ir.BitCast<IR::F32>(GetReg20(insn));
}

1
src/shader_recompiler/frontend/maxwell/translate/impl/impl.h
View file

@ -353,6 +353,7 @@ public:
[[nodiscard]] IR::U32 GetReg8(u64 insn);
[[nodiscard]] IR::U32 GetReg20(u64 insn);
[[nodiscard]] IR::U32 GetReg39(u64 insn);
[[nodiscard]] IR::F32 GetFloatReg8(u64 insn);
[[nodiscard]] IR::F32 GetFloatReg20(u64 insn);
[[nodiscard]] IR::F32 GetFloatReg39(u64 insn);
[[nodiscard]] IR::F64 GetDoubleReg20(u64 insn);

4
src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
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@ -89,10 +89,6 @@ void TranslatorVisitor::FCHK_imm(u64) {
ThrowNotImplemented(Opcode::FCHK_imm);
}
void TranslatorVisitor::FSWZADD(u64) {
ThrowNotImplemented(Opcode::FSWZADD);
}
void TranslatorVisitor::GETCRSPTR(u64) {
ThrowNotImplemented(Opcode::GETCRSPTR);
}