Shader: Remove OutputRegisters struct
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9ea5eacf91
commit
6fa3687afc
4 changed files with 17 additions and 22 deletions
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@ -73,19 +73,13 @@ struct OutputVertex {
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ret.Lerp(factor, v1);
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return ret;
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}
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static OutputVertex FromRegisters(Math::Vec4<float24> output_regs[16], const Regs& regs,
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u32 output_mask);
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};
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static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
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static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has invalid size");
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struct OutputRegisters {
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OutputRegisters() = default;
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alignas(16) Math::Vec4<float24> value[16];
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OutputVertex ToVertex(const Regs::ShaderConfig& config) const;
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};
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static_assert(std::is_pod<OutputRegisters>::value, "Structure is not POD");
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/**
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* This structure contains the state information that needs to be unique for a shader unit. The 3DS
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* has four shader units that process shaders in parallel. At the present, Citra only implements a
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@ -98,11 +92,10 @@ struct UnitState {
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// required to be 16-byte aligned.
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alignas(16) Math::Vec4<float24> input[16];
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alignas(16) Math::Vec4<float24> temporary[16];
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alignas(16) Math::Vec4<float24> output[16];
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} registers;
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static_assert(std::is_pod<Registers>::value, "Structure is not POD");
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OutputRegisters output_registers;
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bool conditional_code[2];
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// Two Address registers and one loop counter
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@ -128,7 +121,7 @@ struct UnitState {
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static size_t OutputOffset(const DestRegister& reg) {
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switch (reg.GetRegisterType()) {
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case RegisterType::Output:
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return offsetof(UnitState, output_registers.value) +
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return offsetof(UnitState, registers.output) +
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reg.GetIndex() * sizeof(Math::Vec4<float24>);
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case RegisterType::Temporary:
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