shader: Primitive Vulkan integration

src/shader_recompiler/frontend/ir/basic_block.cpp

@@ -127,6 +127,8 @@ static std::string ArgToIndex(const std::map<const Block*, size_t>& block_to_ind
         return fmt::format("#{}", arg.U32());
     case Type::U64:
         return fmt::format("#{}", arg.U64());
+    case Type::F32:
+        return fmt::format("#{}", arg.F32());
     case Type::Reg:
         return fmt::format("{}", arg.Reg());
     case Type::Pred:

src/shader_recompiler/frontend/ir/post_order.cpp

@@ -28,7 +28,7 @@ BlockList PostOrder(const BlockList& blocks) {
         if (!visited.insert(branch).second) {
             return false;
         }
-        // Calling push_back twice is faster than insert on msvc
+        // Calling push_back twice is faster than insert on MSVC
         block_stack.push_back(block);
         block_stack.push_back(branch);
         return true;

src/shader_recompiler/frontend/maxwell/program.cpp

@@ -69,7 +69,7 @@ IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Blo
         Optimization::VerificationPass(function);
     }
     Optimization::CollectShaderInfoPass(program);
-    //*/
+    fmt::print(stdout, "{}\n", IR::DumpProgram(program));
     return program;
 }
 

src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp

@@ -24,6 +24,14 @@ void TranslatorVisitor::F(IR::Reg dest_reg, const IR::F32& value) {
     X(dest_reg, ir.BitCast<IR::U32>(value));
 }
 
+IR::U32 TranslatorVisitor::GetReg8(u64 insn) {
+    union {
+        u64 raw;
+        BitField<8, 8, IR::Reg> index;
+    } const reg{insn};
+    return X(reg.index);
+}
+
 IR::U32 TranslatorVisitor::GetReg20(u64 insn) {
     union {
         u64 raw;

src/shader_recompiler/frontend/maxwell/translate/impl/impl.h

@@ -301,6 +301,7 @@ public:
     void X(IR::Reg dest_reg, const IR::U32& value);
     void F(IR::Reg dest_reg, const IR::F32& value);
 
+    [[nodiscard]] IR::U32 GetReg8(u64 insn);
     [[nodiscard]] IR::U32 GetReg20(u64 insn);
     [[nodiscard]] IR::U32 GetReg39(u64 insn);
     [[nodiscard]] IR::F32 GetReg20F(u64 insn);

src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp

@@ -10,36 +10,35 @@
 
 namespace Shader::Maxwell {
 namespace {
-union MOV {
-    u64 raw;
-    BitField<0, 8, IR::Reg> dest_reg;
-    BitField<20, 8, IR::Reg> src_reg;
-    BitField<39, 4, u64> mask;
-};
+void MOV(TranslatorVisitor& v, u64 insn, const IR::U32& src, bool is_mov32i = false) {
+    union {
+        u64 raw;
+        BitField<0, 8, IR::Reg> dest_reg;
+        BitField<39, 4, u64> mask;
+        BitField<12, 4, u64> mov32i_mask;
+    } const mov{insn};
 
-void CheckMask(MOV mov) {
-    if (mov.mask != 0xf) {
+    if ((is_mov32i ? mov.mov32i_mask : mov.mask) != 0xf) {
         throw NotImplementedException("Non-full move mask");
     }
+    v.X(mov.dest_reg, src);
 }
 } // Anonymous namespace
 
 void TranslatorVisitor::MOV_reg(u64 insn) {
-    const MOV mov{insn};
-    CheckMask(mov);
-    X(mov.dest_reg, X(mov.src_reg));
+    MOV(*this, insn, GetReg8(insn));
 }
 
 void TranslatorVisitor::MOV_cbuf(u64 insn) {
-    const MOV mov{insn};
-    CheckMask(mov);
-    X(mov.dest_reg, GetCbuf(insn));
+    MOV(*this, insn, GetCbuf(insn));
 }
 
 void TranslatorVisitor::MOV_imm(u64 insn) {
-    const MOV mov{insn};
-    CheckMask(mov);
-    X(mov.dest_reg, GetImm20(insn));
+    MOV(*this, insn, GetImm20(insn));
+}
+
+void TranslatorVisitor::MOV32I(u64 insn) {
+    MOV(*this, insn, GetImm32(insn), true);
 }
 
 } // namespace Shader::Maxwell

src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp

@@ -617,10 +617,6 @@ void TranslatorVisitor::MEMBAR(u64) {
     ThrowNotImplemented(Opcode::MEMBAR);
 }
 
-void TranslatorVisitor::MOV32I(u64) {
-    ThrowNotImplemented(Opcode::MOV32I);
-}
-
 void TranslatorVisitor::NOP(u64) {
     ThrowNotImplemented(Opcode::NOP);
 }