Mirrors/yuzu
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

shader: Implement SEL

Browse source
This commit is contained in:
ameerj 2021-02-24 20:31:15 -05:00
parent 726625cf50
commit 8810c88b7e
4 changed files with 53 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

12
src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
View file

@ -729,18 +729,6 @@ void TranslatorVisitor::SAM(u64) {
ThrowNotImplemented(Opcode::SAM);
}
void TranslatorVisitor::SEL_reg(u64) {
ThrowNotImplemented(Opcode::SEL_reg);
}
void TranslatorVisitor::SEL_cbuf(u64) {
ThrowNotImplemented(Opcode::SEL_cbuf);
}
void TranslatorVisitor::SEL_imm(u64) {
ThrowNotImplemented(Opcode::SEL_imm);
}
void TranslatorVisitor::SETCRSPTR(u64) {
ThrowNotImplemented(Opcode::SETCRSPTR);
}

44
src/shader_recompiler/frontend/maxwell/translate/impl/select_source_with_predicate.cpp Normal file
View file

@ -0,0 +1,44 @@
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "common/bit_field.h"
#include "common/common_types.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
namespace Shader::Maxwell {
namespace {
void SEL(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
union {
u64 raw;
BitField<0, 8, IR::Reg> dest_reg;
BitField<8, 8, IR::Reg> op_a;
BitField<39, 3, IR::Pred> pred;
BitField<42, 1, u64> neg_pred;
} const sel{insn};
const IR::U1 pred = v.ir.GetPred(sel.pred);
IR::U32 op_a{v.X(sel.op_a)};
IR::U32 op_b{src};
if (sel.neg_pred != 0) {
std::swap(op_a, op_b);
}
const IR::U32 result{v.ir.Select(pred, op_a, op_b)};
v.X(sel.dest_reg, result);
}
} // Anonymous namespace
void TranslatorVisitor::SEL_reg(u64 insn) {
SEL(*this, insn, GetReg20(insn));
}
void TranslatorVisitor::SEL_cbuf(u64 insn) {
SEL(*this, insn, GetCbuf(insn));
}
void TranslatorVisitor::SEL_imm(u64 insn) {
SEL(*this, insn, GetImm20(insn));
}
} // namespace Shader::Maxwell