Remove unused PrepareReschedule function
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7f77aafe41
commit
91a6df0361
7 changed files with 0 additions and 20 deletions
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@ -174,9 +174,6 @@ public:
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/// Clears the exclusive monitor's state.
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virtual void ClearExclusiveState() = 0;
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/// Prepare core for thread reschedule (if needed to correctly handle state)
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virtual void PrepareReschedule() = 0;
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/// Signal an interrupt and ask the core to halt as soon as possible.
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virtual void SignalInterrupt() = 0;
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@ -327,10 +327,6 @@ void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
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jit.load()->LoadContext(context);
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}
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void ARM_Dynarmic_32::PrepareReschedule() {
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jit.load()->HaltExecution(break_loop);
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}
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void ARM_Dynarmic_32::SignalInterrupt() {
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jit.load()->HaltExecution(break_loop);
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}
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@ -57,7 +57,6 @@ public:
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void LoadContext(const ThreadContext32& ctx) override;
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void LoadContext(const ThreadContext64& ctx) override {}
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void PrepareReschedule() override;
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void SignalInterrupt() override;
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void ClearExclusiveState() override;
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@ -395,10 +395,6 @@ void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
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SetTPIDR_EL0(ctx.tpidr);
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}
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void ARM_Dynarmic_64::PrepareReschedule() {
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jit.load()->HaltExecution(break_loop);
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}
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void ARM_Dynarmic_64::SignalInterrupt() {
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jit.load()->HaltExecution(break_loop);
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}
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@ -51,7 +51,6 @@ public:
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void LoadContext(const ThreadContext32& ctx) override {}
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void LoadContext(const ThreadContext64& ctx) override;
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void PrepareReschedule() override;
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void SignalInterrupt() override;
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void ClearExclusiveState() override;
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