vfp: Actually make the code somewhat readable
This commit is contained in:
Lioncash
parent
4bf803579f
commit
9c7f2570f7
5 changed files with 1053 additions and 1664 deletions
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@ -32,8 +32,7 @@
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//ARMul_State* persistent_state; /* function calls from SoftFloat lib don't have an access to ARMul_state. */
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unsigned
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VFPInit (ARMul_State *state)
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unsigned VFPInit(ARMul_State* state)
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{
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state->VFP[VFP_OFFSET(VFP_FPSID)] = VFP_FPSID_IMPLMEN<<24 | VFP_FPSID_SW<<23 | VFP_FPSID_SUBARCH<<16 |
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VFP_FPSID_PARTNUM<<8 | VFP_FPSID_VARIANT<<4 | VFP_FPSID_REVISION;
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@ -46,8 +45,7 @@ VFPInit (ARMul_State *state)
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return 0;
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}
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unsigned
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VFPMRC (ARMul_State * state, unsigned type, u32 instr, u32 * value)
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unsigned VFPMRC(ARMul_State* state, unsigned type, u32 instr, u32* value)
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{
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/* MRC<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>} */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -61,10 +59,21 @@ VFPMRC (ARMul_State * state, unsigned type, u32 instr, u32 * value)
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 10 || CoProc == 11) {
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#define VFP_MRC_TRANS
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_MRC_TRANS
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if (CoProc == 10 || CoProc == 11)
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{
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if (OPC_1 == 0x0 && CRm == 0 && (OPC_2 & 0x3) == 0)
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{
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/* VMOV r to s */
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/* Transfering Rt is not mandatory, as the value of interest is pointed by value */
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VMOVBRS(state, BIT(20), Rt, BIT(7)|CRn<<1, value);
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return ARMul_DONE;
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}
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if (OPC_1 == 0x7 && CRm == 0 && OPC_2 == 0)
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{
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VMRS(state, CRn, Rt, value);
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return ARMul_DONE;
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}
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}
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DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
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instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
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@ -72,8 +81,7 @@ VFPMRC (ARMul_State * state, unsigned type, u32 instr, u32 * value)
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return ARMul_CANT;
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}
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unsigned
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VFPMCR (ARMul_State * state, unsigned type, u32 instr, u32 value)
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unsigned VFPMCR(ARMul_State* state, unsigned type, u32 instr, u32 value)
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{
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/* MCR<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>} */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -86,10 +94,33 @@ VFPMCR (ARMul_State * state, unsigned type, u32 instr, u32 value)
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/* TODO check access permission */
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 10 || CoProc == 11) {
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#define VFP_MCR_TRANS
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_MCR_TRANS
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if (CoProc == 10 || CoProc == 11)
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{
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if (OPC_1 == 0x0 && CRm == 0 && (OPC_2 & 0x3) == 0)
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{
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/* VMOV s to r */
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/* Transfering Rt is not mandatory, as the value of interest is pointed by value */
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VMOVBRS(state, BIT(20), Rt, BIT(7)|CRn<<1, &value);
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return ARMul_DONE;
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}
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if (OPC_1 == 0x7 && CRm == 0 && OPC_2 == 0)
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{
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VMSR(state, CRn, Rt);
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return ARMul_DONE;
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}
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if ((OPC_1 & 0x4) == 0 && CoProc == 11 && CRm == 0)
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{
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VFP_DEBUG_UNIMPLEMENTED(VMOVBRC);
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return ARMul_DONE;
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}
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if (CoProc == 11 && CRm == 0)
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{
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VFP_DEBUG_UNIMPLEMENTED(VMOVBCR);
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return ARMul_DONE;
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}
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}
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DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
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instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
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@ -97,8 +128,7 @@ VFPMCR (ARMul_State * state, unsigned type, u32 instr, u32 value)
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return ARMul_CANT;
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}
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unsigned
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VFPMRRC (ARMul_State * state, unsigned type, u32 instr, u32 * value1, u32 * value2)
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unsigned VFPMRRC(ARMul_State* state, unsigned type, u32 instr, u32* value1, u32* value2)
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{
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/* MCRR<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm> */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -107,10 +137,20 @@ VFPMRRC (ARMul_State * state, unsigned type, u32 instr, u32 * value1, u32 * valu
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int Rt2 = BITS (16, 19);
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int CRm = BITS (0, 3);
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if (CoProc == 10 || CoProc == 11) {
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#define VFP_MRRC_TRANS
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_MRRC_TRANS
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if (CoProc == 10 || CoProc == 11)
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{
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if (CoProc == 10 && (OPC_1 & 0xD) == 1)
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{
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VFP_DEBUG_UNIMPLEMENTED(VMOVBRRSS);
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return ARMul_DONE;
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}
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if (CoProc == 11 && (OPC_1 & 0xD) == 1)
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{
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/* Transfering Rt and Rt2 is not mandatory, as the value of interest is pointed by value1 and value2 */
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VMOVBRRD(state, BIT(20), Rt, Rt2, BIT(5)<<4|CRm, value1, value2);
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return ARMul_DONE;
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}
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}
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DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
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instr, CoProc, OPC_1, Rt, Rt2, CRm);
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@ -118,8 +158,7 @@ VFPMRRC (ARMul_State * state, unsigned type, u32 instr, u32 * value1, u32 * valu
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return ARMul_CANT;
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}
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unsigned
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VFPMCRR (ARMul_State * state, unsigned type, u32 instr, u32 value1, u32 value2)
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unsigned VFPMCRR(ARMul_State* state, unsigned type, u32 instr, u32 value1, u32 value2)
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{
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/* MCRR<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm> */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -132,10 +171,20 @@ VFPMCRR (ARMul_State * state, unsigned type, u32 instr, u32 value1, u32 value2)
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 11 || CoProc == 10) {
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#define VFP_MCRR_TRANS
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_MCRR_TRANS
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if (CoProc == 11 || CoProc == 10)
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{
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if (CoProc == 10 && (OPC_1 & 0xD) == 1)
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{
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VFP_DEBUG_UNIMPLEMENTED(VMOVBRRSS);
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return ARMul_DONE;
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}
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if (CoProc == 11 && (OPC_1 & 0xD) == 1)
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{
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/* Transfering Rt and Rt2 is not mandatory, as the value of interest is pointed by value1 and value2 */
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VMOVBRRD(state, BIT(20), Rt, Rt2, BIT(5)<<4|CRm, &value1, &value2);
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return ARMul_DONE;
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}
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}
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DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
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instr, CoProc, OPC_1, Rt, Rt2, CRm);
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@ -143,8 +192,7 @@ VFPMCRR (ARMul_State * state, unsigned type, u32 instr, u32 value1, u32 value2)
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return ARMul_CANT;
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}
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unsigned
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VFPSTC (ARMul_State * state, unsigned type, u32 instr, u32 * value)
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unsigned VFPSTC(ARMul_State* state, unsigned type, u32 instr, u32 * value)
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{
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/* STC{L}<c> <coproc>,<CRd>,[<Rn>],<option> */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -175,9 +223,17 @@ VFPSTC (ARMul_State * state, unsigned type, u32 instr, u32 * value)
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}
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#endif
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#define VFP_STC_TRANS
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_STC_TRANS
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if (P == 1 && W == 0)
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{
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return VSTR(state, type, instr, value);
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}
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if (P == 1 && U == 0 && W == 1 && Rn == 0xD)
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{
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return VPUSH(state, type, instr, value);
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}
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return VSTM(state, type, instr, value);
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}
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DEBUG("Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
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instr, CoProc, CRd, Rn, imm8, P, U, D, W);
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@ -185,8 +241,7 @@ VFPSTC (ARMul_State * state, unsigned type, u32 instr, u32 * value)
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return ARMul_CANT;
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}
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unsigned
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VFPLDC (ARMul_State * state, unsigned type, u32 instr, u32 value)
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unsigned VFPLDC(ARMul_State* state, unsigned type, u32 instr, u32 value)
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{
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/* LDC{L}<c> <coproc>,<CRd>,[<Rn>] */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -204,10 +259,19 @@ VFPLDC (ARMul_State * state, unsigned type, u32 instr, u32 value)
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DEBUG("In %s, UNDEFINED\n", __FUNCTION__);
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exit(-1);
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}
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if (CoProc == 10 || CoProc == 11) {
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#define VFP_LDC_TRANS
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_LDC_TRANS
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if (CoProc == 10 || CoProc == 11)
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{
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if (P == 1 && W == 0)
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{
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return VLDR(state, type, instr, value);
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}
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if (P == 0 && U == 1 && W == 1 && Rn == 0xD)
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{
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return VPOP(state, type, instr, value);
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}
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return VLDM(state, type, instr, value);
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}
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DEBUG("Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
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instr, CoProc, CRd, Rn, imm8, P, U, D, W);
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@ -215,8 +279,7 @@ VFPLDC (ARMul_State * state, unsigned type, u32 instr, u32 value)
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return ARMul_CANT;
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}
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unsigned
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VFPCDP (ARMul_State * state, unsigned type, u32 instr)
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unsigned VFPCDP(ARMul_State* state, unsigned type, u32 instr)
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{
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/* CDP<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2> */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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@ -275,10 +338,83 @@ VFPCDP (ARMul_State * state, unsigned type, u32 instr)
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 10 || CoProc == 11) {
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#define VFP_CDP_TRANS
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_CDP_TRANS
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if (CoProc == 10 || CoProc == 11)
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{
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if ((OPC_1 & 0xB) == 0 && (OPC_2 & 0x2) == 0)
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DBG("VMLA :\n");
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if ((OPC_1 & 0xB) == 0 && (OPC_2 & 0x2) == 2)
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DBG("VMLS :\n");
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if ((OPC_1 & 0xB) == 1 && (OPC_2 & 0x2) == 2)
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DBG("VNMLA :\n");
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if ((OPC_1 & 0xB) == 1 && (OPC_2 & 0x2) == 0)
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DBG("VNMLS :\n");
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if ((OPC_1 & 0xB) == 2 && (OPC_2 & 0x2) == 2)
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DBG("VNMUL :\n");
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if ((OPC_1 & 0xB) == 2 && (OPC_2 & 0x2) == 0)
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DBG("VMUL :\n");
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if ((OPC_1 & 0xB) == 3 && (OPC_2 & 0x2) == 0)
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DBG("VADD :\n");
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if ((OPC_1 & 0xB) == 3 && (OPC_2 & 0x2) == 2)
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DBG("VSUB :\n");
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if ((OPC_1 & 0xB) == 0xA && (OPC_2 & 0x2) == 0)
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DBG("VDIV :\n");
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if ((OPC_1 & 0xB) == 0xB && BITS(4, 7) == 0)
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{
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unsigned int single = BIT(8) == 0;
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unsigned int d = (single ? BITS(12,15)<<1 | BIT(22) : BITS(12,15) | BIT(22)<<4);
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unsigned int imm;
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instr = BITS(16, 19) << 4 | BITS(0, 3); /* FIXME dirty workaround to get a correct imm */
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if (single)
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imm = BIT(7)<<31 | (BIT(6)==0)<<30 | (BIT(6) ? 0x1f : 0)<<25 | BITS(0, 5)<<19;
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else
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imm = BIT(7)<<31 | (BIT(6)==0)<<30 | (BIT(6) ? 0xff : 0)<<22 | BITS(0, 5)<<16;
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VMOVI(state, single, d, imm);
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return ARMul_DONE;
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}
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if ((OPC_1 & 0xB) == 0xB && CRn == 0 && (OPC_2 & 0x6) == 0x2)
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{
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unsigned int single = BIT(8) == 0;
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unsigned int d = (single ? BITS(12,15)<<1 | BIT(22) : BITS(12,15) | BIT(22)<<4);
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unsigned int m = (single ? BITS( 0, 3)<<1 | BIT( 5) : BITS( 0, 3) | BIT( 5)<<4);;
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VMOVR(state, single, d, m);
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return ARMul_DONE;
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}
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if ((OPC_1 & 0xB) == 0xB && CRn == 0 && (OPC_2 & 0x7) == 6)
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DBG("VABS :\n");
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if ((OPC_1 & 0xB) == 0xB && CRn == 1 && (OPC_2 & 0x7) == 2)
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DBG("VNEG :\n");
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if ((OPC_1 & 0xB) == 0xB && CRn == 1 && (OPC_2 & 0x7) == 6)
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DBG("VSQRT :\n");
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if ((OPC_1 & 0xB) == 0xB && CRn == 4 && (OPC_2 & 0x2) == 2)
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DBG("VCMP(1) :\n");
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if ((OPC_1 & 0xB) == 0xB && CRn == 5 && (OPC_2 & 0x2) == 2 && CRm == 0)
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DBG("VCMP(2) :\n");
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if ((OPC_1 & 0xB) == 0xB && CRn == 7 && (OPC_2 & 0x6) == 6)
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DBG("VCVT(BDS) :\n");
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if ((OPC_1 & 0xB) == 0xB && CRn >= 0xA && (OPC_2 & 0x2) == 2)
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DBG("VCVT(BFF) :\n");
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if ((OPC_1 & 0xB) == 0xB && CRn > 7 && (OPC_2 & 0x2) == 2)
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DBG("VCVT(BFI) :\n");
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int exceptions = 0;
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if (CoProc == 10)
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@ -296,23 +432,93 @@ VFPCDP (ARMul_State * state, unsigned type, u32 instr)
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/* ----------- MRC ------------ */
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#define VFP_MRC_IMPL
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_MRC_IMPL
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#define VFP_MRRC_IMPL
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_MRRC_IMPL
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void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value)
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{
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DBG("VMOV(BRS) :\n");
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if (to_arm)
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{
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DBG("\tr%d <= s%d=[%x]\n", t, n, state->ExtReg[n]);
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*value = state->ExtReg[n];
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}
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else
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{
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DBG("\ts%d <= r%d=[%x]\n", n, t, *value);
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state->ExtReg[n] = *value;
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}
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}
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void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value)
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{
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DBG("VMRS :");
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if (reg == 1)
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{
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if (Rt != 15)
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{
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*value = state->VFP[VFP_OFFSET(VFP_FPSCR)];
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DBG("\tr%d <= fpscr[%08x]\n", Rt, state->VFP[VFP_OFFSET(VFP_FPSCR)]);
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}
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else
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{
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*value = state->VFP[VFP_OFFSET(VFP_FPSCR)] ;
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DBG("\tflags <= fpscr[%1xxxxxxxx]\n", state->VFP[VFP_OFFSET(VFP_FPSCR)]>>28);
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}
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}
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else
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{
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switch (reg)
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{
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case 0:
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*value = state->VFP[VFP_OFFSET(VFP_FPSID)];
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DBG("\tr%d <= fpsid[%08x]\n", Rt, state->VFP[VFP_OFFSET(VFP_FPSID)]);
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break;
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case 6:
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/* MVFR1, VFPv3 only ? */
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DBG("\tr%d <= MVFR1 unimplemented\n", Rt);
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break;
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case 7:
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/* MVFR0, VFPv3 only? */
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DBG("\tr%d <= MVFR0 unimplemented\n", Rt);
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break;
|
||||
case 8:
|
||||
*value = state->VFP[VFP_OFFSET(VFP_FPEXC)];
|
||||
DBG("\tr%d <= fpexc[%08x]\n", Rt, state->VFP[VFP_OFFSET(VFP_FPEXC)]);
|
||||
break;
|
||||
default:
|
||||
DBG("\tSUBARCHITECTURE DEFINED\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
|
||||
{
|
||||
DBG("VMOV(BRRD) :\n");
|
||||
if (to_arm)
|
||||
{
|
||||
DBG("\tr[%d-%d] <= s[%d-%d]=[%x-%x]\n", t2, t, n*2+1, n*2, state->ExtReg[n*2+1], state->ExtReg[n*2]);
|
||||
*value2 = state->ExtReg[n*2+1];
|
||||
*value1 = state->ExtReg[n*2];
|
||||
}
|
||||
else
|
||||
{
|
||||
DBG("\ts[%d-%d] <= r[%d-%d]=[%x-%x]\n", n*2+1, n*2, t2, t, *value2, *value1);
|
||||
state->ExtReg[n*2+1] = *value2;
|
||||
state->ExtReg[n*2] = *value1;
|
||||
}
|
||||
}
|
||||
|
||||
/* ----------- MCR ------------ */
|
||||
#define VFP_MCR_IMPL
|
||||
#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
|
||||
#undef VFP_MCR_IMPL
|
||||
|
||||
#define VFP_MCRR_IMPL
|
||||
#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
|
||||
#undef VFP_MCRR_IMPL
|
||||
void VMSR(ARMul_State* state, ARMword reg, ARMword Rt)
|
||||
{
|
||||
if (reg == 1)
|
||||
{
|
||||
DBG("VMSR :\tfpscr <= r%d=[%x]\n", Rt, state->Reg[Rt]);
|
||||
state->VFP[VFP_OFFSET(VFP_FPSCR)] = state->Reg[Rt];
|
||||
}
|
||||
else if (reg == 8)
|
||||
{
|
||||
DBG("VMSR :\tfpexc <= r%d=[%x]\n", Rt, state->Reg[Rt]);
|
||||
state->VFP[VFP_OFFSET(VFP_FPEXC)] = state->Reg[Rt];
|
||||
}
|
||||
}
|
||||
|
||||
/* Memory operation are not inlined, as old Interpreter and Fast interpreter
|
||||
don't have the same memory operation interface.
|
||||
|
|
@ -322,21 +528,342 @@ VFPCDP (ARMul_State * state, unsigned type, u32 instr)
|
|||
of vfp instructions in old interpreter and fast interpreter are separate. */
|
||||
|
||||
/* ----------- STC ------------ */
|
||||
#define VFP_STC_IMPL
|
||||
#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
|
||||
#undef VFP_STC_IMPL
|
||||
int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value)
|
||||
{
|
||||
static int i = 0;
|
||||
static int single_reg, add, d, n, imm32, regs;
|
||||
if (type == ARMul_FIRST)
|
||||
{
|
||||
single_reg = BIT(8) == 0; /* Double precision */
|
||||
add = BIT(23); /* */
|
||||
imm32 = BITS(0,7)<<2; /* may not be used */
|
||||
d = single_reg ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */
|
||||
n = BITS(16, 19); /* destination register */
|
||||
|
||||
DBG("VSTR :\n");
|
||||
|
||||
i = 0;
|
||||
regs = 1;
|
||||
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else if (type == ARMul_DATA)
|
||||
{
|
||||
if (single_reg)
|
||||
{
|
||||
*value = state->ExtReg[d+i];
|
||||
DBG("\taddr[?] <= s%d=[%x]\n", d+i, state->ExtReg[d+i]);
|
||||
i++;
|
||||
if (i < regs)
|
||||
return ARMul_INC;
|
||||
else
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* FIXME Careful of endianness, may need to rework this */
|
||||
*value = state->ExtReg[d*2+i];
|
||||
DBG("\taddr[?] <= s[%d]=[%x]\n", d*2+i, state->ExtReg[d*2+i]);
|
||||
i++;
|
||||
if (i < regs*2)
|
||||
return ARMul_INC;
|
||||
else
|
||||
return ARMul_DONE;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value)
|
||||
{
|
||||
static int i = 0;
|
||||
static int single_regs, add, wback, d, n, imm32, regs;
|
||||
if (type == ARMul_FIRST)
|
||||
{
|
||||
single_regs = BIT(8) == 0; /* Single precision */
|
||||
d = single_regs ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */
|
||||
imm32 = BITS(0,7)<<2; /* may not be used */
|
||||
regs = single_regs ? BITS(0, 7) : BITS(1, 7); /* FSTMX if regs is odd */
|
||||
|
||||
DBG("VPUSH :\n");
|
||||
DBG("\tsp[%x]", state->Reg[R13]);
|
||||
state->Reg[R13] = state->Reg[R13] - imm32;
|
||||
DBG("=>[%x]\n", state->Reg[R13]);
|
||||
|
||||
i = 0;
|
||||
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else if (type == ARMul_DATA)
|
||||
{
|
||||
if (single_regs)
|
||||
{
|
||||
*value = state->ExtReg[d + i];
|
||||
DBG("\taddr[?] <= s%d=[%x]\n", d+i, state->ExtReg[d + i]);
|
||||
i++;
|
||||
if (i < regs)
|
||||
return ARMul_INC;
|
||||
else
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* FIXME Careful of endianness, may need to rework this */
|
||||
*value = state->ExtReg[d*2 + i];
|
||||
DBG("\taddr[?] <= s[%d]=[%x]\n", d*2 + i, state->ExtReg[d*2 + i]);
|
||||
i++;
|
||||
if (i < regs*2)
|
||||
return ARMul_INC;
|
||||
else
|
||||
return ARMul_DONE;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value)
|
||||
{
|
||||
static int i = 0;
|
||||
static int single_regs, add, wback, d, n, imm32, regs;
|
||||
if (type == ARMul_FIRST)
|
||||
{
|
||||
single_regs = BIT(8) == 0; /* Single precision */
|
||||
add = BIT(23); /* */
|
||||
wback = BIT(21); /* write-back */
|
||||
d = single_regs ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */
|
||||
n = BITS(16, 19); /* destination register */
|
||||
imm32 = BITS(0,7) * 4; /* may not be used */
|
||||
regs = single_regs ? BITS(0, 7) : BITS(0, 7)>>1; /* FSTMX if regs is odd */
|
||||
|
||||
DBG("VSTM :\n");
|
||||
|
||||
if (wback) {
|
||||
state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32);
|
||||
DBG("\twback r%d[%x]\n", n, state->Reg[n]);
|
||||
}
|
||||
|
||||
i = 0;
|
||||
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else if (type == ARMul_DATA)
|
||||
{
|
||||
if (single_regs)
|
||||
{
|
||||
*value = state->ExtReg[d + i];
|
||||
DBG("\taddr[?] <= s%d=[%x]\n", d+i, state->ExtReg[d + i]);
|
||||
i++;
|
||||
if (i < regs)
|
||||
return ARMul_INC;
|
||||
else
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* FIXME Careful of endianness, may need to rework this */
|
||||
*value = state->ExtReg[d*2 + i];
|
||||
DBG("\taddr[?] <= s[%d]=[%x]\n", d*2 + i, state->ExtReg[d*2 + i]);
|
||||
i++;
|
||||
if (i < regs*2)
|
||||
return ARMul_INC;
|
||||
else
|
||||
return ARMul_DONE;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* ----------- LDC ------------ */
|
||||
#define VFP_LDC_IMPL
|
||||
#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
|
||||
#undef VFP_LDC_IMPL
|
||||
int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value)
|
||||
{
|
||||
static int i = 0;
|
||||
static int single_regs, add, wback, d, n, imm32, regs;
|
||||
if (type == ARMul_FIRST)
|
||||
{
|
||||
single_regs = BIT(8) == 0; /* Single precision */
|
||||
d = single_regs ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */
|
||||
imm32 = BITS(0,7)<<2; /* may not be used */
|
||||
regs = single_regs ? BITS(0, 7) : BITS(1, 7); /* FLDMX if regs is odd */
|
||||
|
||||
DBG("VPOP :\n");
|
||||
DBG("\tsp[%x]", state->Reg[R13]);
|
||||
state->Reg[R13] = state->Reg[R13] + imm32;
|
||||
DBG("=>[%x]\n", state->Reg[R13]);
|
||||
|
||||
i = 0;
|
||||
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else if (type == ARMul_TRANSFER)
|
||||
{
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else if (type == ARMul_DATA)
|
||||
{
|
||||
if (single_regs)
|
||||
{
|
||||
state->ExtReg[d + i] = value;
|
||||
DBG("\ts%d <= [%x]\n", d + i, value);
|
||||
i++;
|
||||
if (i < regs)
|
||||
return ARMul_INC;
|
||||
else
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* FIXME Careful of endianness, may need to rework this */
|
||||
state->ExtReg[d*2 + i] = value;
|
||||
DBG("\ts%d <= [%x]\n", d*2 + i, value);
|
||||
i++;
|
||||
if (i < regs*2)
|
||||
return ARMul_INC;
|
||||
else
|
||||
return ARMul_DONE;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value)
|
||||
{
|
||||
static int i = 0;
|
||||
static int single_reg, add, d, n, imm32, regs;
|
||||
if (type == ARMul_FIRST)
|
||||
{
|
||||
single_reg = BIT(8) == 0; /* Double precision */
|
||||
add = BIT(23); /* */
|
||||
imm32 = BITS(0,7)<<2; /* may not be used */
|
||||
d = single_reg ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */
|
||||
n = BITS(16, 19); /* destination register */
|
||||
|
||||
DBG("VLDR :\n");
|
||||
|
||||
i = 0;
|
||||
regs = 1;
|
||||
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else if (type == ARMul_TRANSFER)
|
||||
{
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else if (type == ARMul_DATA)
|
||||
{
|
||||
if (single_reg)
|
||||
{
|
||||
state->ExtReg[d+i] = value;
|
||||
DBG("\ts%d <= [%x]\n", d+i, value);
|
||||
i++;
|
||||
if (i < regs)
|
||||
return ARMul_INC;
|
||||
else
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* FIXME Careful of endianness, may need to rework this */
|
||||
state->ExtReg[d*2+i] = value;
|
||||
DBG("\ts[%d] <= [%x]\n", d*2+i, value);
|
||||
i++;
|
||||
if (i < regs*2)
|
||||
return ARMul_INC;
|
||||
else
|
||||
return ARMul_DONE;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
|
||||
{
|
||||
static int i = 0;
|
||||
static int single_regs, add, wback, d, n, imm32, regs;
|
||||
if (type == ARMul_FIRST)
|
||||
{
|
||||
single_regs = BIT(8) == 0; /* Single precision */
|
||||
add = BIT(23); /* */
|
||||
wback = BIT(21); /* write-back */
|
||||
d = single_regs ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */
|
||||
n = BITS(16, 19); /* destination register */
|
||||
imm32 = BITS(0,7) * 4; /* may not be used */
|
||||
regs = single_regs ? BITS(0, 7) : BITS(0, 7)>>1; /* FLDMX if regs is odd */
|
||||
|
||||
DBG("VLDM :\n");
|
||||
|
||||
if (wback) {
|
||||
state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32);
|
||||
DBG("\twback r%d[%x]\n", n, state->Reg[n]);
|
||||
}
|
||||
|
||||
i = 0;
|
||||
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else if (type == ARMul_DATA)
|
||||
{
|
||||
if (single_regs)
|
||||
{
|
||||
state->ExtReg[d + i] = value;
|
||||
DBG("\ts%d <= [%x] addr[?]\n", d+i, state->ExtReg[d + i]);
|
||||
i++;
|
||||
if (i < regs)
|
||||
return ARMul_INC;
|
||||
else
|
||||
return ARMul_DONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* FIXME Careful of endianness, may need to rework this */
|
||||
state->ExtReg[d*2 + i] = value;
|
||||
DBG("\ts[%d] <= [%x] addr[?]\n", d*2 + i, state->ExtReg[d*2 + i]);
|
||||
i++;
|
||||
if (i < regs*2)
|
||||
return ARMul_INC;
|
||||
else
|
||||
return ARMul_DONE;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* ----------- CDP ------------ */
|
||||
#define VFP_CDP_IMPL
|
||||
#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
|
||||
#undef VFP_CDP_IMPL
|
||||
void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm)
|
||||
{
|
||||
DBG("VMOV(I) :\n");
|
||||
|
||||
if (single)
|
||||
{
|
||||
DBG("\ts%d <= [%x]\n", d, imm);
|
||||
state->ExtReg[d] = imm;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check endian please */
|
||||
DBG("\ts[%d-%d] <= [%x-%x]\n", d*2+1, d*2, imm, 0);
|
||||
state->ExtReg[d*2+1] = imm;
|
||||
state->ExtReg[d*2] = 0;
|
||||
}
|
||||
}
|
||||
void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword m)
|
||||
{
|
||||
DBG("VMOV(R) :\n");
|
||||
|
||||
if (single)
|
||||
{
|
||||
DBG("\ts%d <= s%d[%x]\n", d, m, state->ExtReg[m]);
|
||||
state->ExtReg[d] = state->ExtReg[m];
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check endian please */
|
||||
DBG("\ts[%d-%d] <= s[%d-%d][%x-%x]\n", d*2+1, d*2, m*2+1, m*2, state->ExtReg[m*2+1], state->ExtReg[m*2]);
|
||||
state->ExtReg[d*2+1] = state->ExtReg[m*2+1];
|
||||
state->ExtReg[d*2] = state->ExtReg[m*2];
|
||||
}
|
||||
}
|
||||
|
||||
/* Miscellaneous functions */
|
||||
int32_t vfp_get_float(arm_core_t* state, unsigned int reg)
|
||||
|
|
@ -366,8 +893,6 @@ void vfp_put_double(arm_core_t* state, uint64_t val, unsigned int reg)
|
|||
state->ExtReg[reg*2+1] = (uint32_t) (val>>32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Process bitmask of exception conditions. (from vfpmodule.c)
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -27,6 +27,12 @@
|
|||
|
||||
#include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */
|
||||
|
||||
#define VFP_DEBUG_TRANSLATE DBG("in func %s, %x\n", __FUNCTION__, inst);
|
||||
#define VFP_DEBUG_UNIMPLEMENTED(x) printf("in func %s, " #x " unimplemented\n", __FUNCTION__); exit(-1);
|
||||
#define VFP_DEBUG_UNTESTED(x) printf("in func %s, " #x " untested\n", __FUNCTION__);
|
||||
#define CHECK_VFP_ENABLED
|
||||
#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); //if (ret == -1) {printf("VFP CDP FAILURE %x\n", inst_cream->instr); exit(-1);}
|
||||
|
||||
unsigned VFPInit (ARMul_State *state);
|
||||
unsigned VFPMRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value);
|
||||
unsigned VFPMCR (ARMul_State * state, unsigned type, ARMword instr, ARMword value);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
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Add table
Add a link
Reference in a new issue