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Merge remote-tracking branch 'upstream/master' into nx

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# Conflicts:
#	src/core/CMakeLists.txt
#	src/core/arm/dynarmic/arm_dynarmic.cpp
#	src/core/arm/dyncom/arm_dyncom.cpp
#	src/core/hle/kernel/process.cpp
#	src/core/hle/kernel/thread.cpp
#	src/core/hle/kernel/thread.h
#	src/core/hle/kernel/vm_manager.cpp
#	src/core/loader/3dsx.cpp
#	src/core/loader/elf.cpp
#	src/core/loader/ncch.cpp
#	src/core/memory.cpp
#	src/core/memory.h
#	src/core/memory_setup.h
This commit is contained in:
bunnei 2017-10-09 23:56:20 -04:00
commit b1d5db1cf6
241 changed files with 20955 additions and 2730 deletions
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22
src/core/arm/arm_interface.h
View file

@ -5,6 +5,7 @@
#pragma once
#include "common/common_types.h"
#include "core/hle/kernel/vm_manager.h"
#include "core/arm/skyeye_common/arm_regformat.h"
#include "core/arm/skyeye_common/vfp/asm_vfp.h"
@ -19,10 +20,11 @@ public:
u64 sp;
u64 pc;
u64 cpsr;
u64 fpu_registers[64];
u128 fpu_registers[32];
u64 fpscr;
u64 fpexc;
// TODO(bunnei): Fix once we have proper support for tpidrro_el0, etc. in the JIT
VAddr tls_address;
};
@ -41,9 +43,14 @@ public:
Run(1);
}
virtual void MapBackingMemory(VAddr address, size_t size, u8* memory, Kernel::VMAPermission perms) {}
/// Clear all instruction cache
virtual void ClearInstructionCache() = 0;
/// Notify CPU emulation that page tables have changed
virtual void PageTableChanged() = 0;
/**
* Set the Program Counter to an address
* @param addr Address to set PC to
@ -70,6 +77,10 @@ public:
*/
virtual void SetReg(int index, u64 value) = 0;
virtual const u128& GetExtReg(int index) const = 0;
virtual void SetExtReg(int index, u128& value) = 0;
/**
* Gets the value of a VFP register
* @param index Register index (0-31)
@ -128,12 +139,6 @@ public:
virtual void SetTlsAddress(VAddr address) = 0;
/**
* Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time)
* @param ticks Number of ticks to advance the CPU core
*/
virtual void AddTicks(u64 ticks) = 0;
/**
* Saves the current CPU context
* @param ctx Thread context to save
@ -154,9 +159,6 @@ public:
return num_instructions;
}
s64 down_count = 0; ///< A decreasing counter of remaining cycles before the next event,
/// decreased by the cpu run loop
protected:
/**
* Executes the given number of instructions

93
src/core/arm/dynarmic/arm_dynarmic.cpp
View file

@ -16,24 +16,6 @@
static void InterpreterFallback(u64 pc, Dynarmic::Jit* jit, void* user_arg) {
UNIMPLEMENTED_MSG("InterpreterFallback for ARM64 JIT does not exist!");
//ARMul_State* state = static_cast<ARMul_State*>(user_arg);
//state->Reg = jit->Regs();
//state->Cpsr = jit->Cpsr();
//state->Reg[15] = static_cast<u32>(pc);
//state->ExtReg = jit->ExtRegs();
//state->VFP[VFP_FPSCR] = jit->Fpscr();
//state->NumInstrsToExecute = 1;
//InterpreterMainLoop(state);
//bool is_thumb = (state->Cpsr & (1 << 5)) != 0;
//state->Reg[15] &= (is_thumb ? 0xFFFFFFFE : 0xFFFFFFFC);
//jit->Regs() = state->Reg;
//jit->Cpsr() = state->Cpsr;
//jit->ExtRegs() = state->ExtReg;
//jit->SetFpscr(state->VFP[VFP_FPSCR]);
}
static bool IsReadOnlyMemory(u64 vaddr) {
@ -73,11 +55,10 @@ void MemoryWrite64(const u64 addr, const u64 data) {
Memory::Write64(static_cast<VAddr>(addr), data);
}
static Dynarmic::UserCallbacks GetUserCallbacks(
const std::shared_ptr<ARMul_State>& interpeter_state) {
static Dynarmic::UserCallbacks GetUserCallbacks(ARM_Dynarmic* this_) {
Dynarmic::UserCallbacks user_callbacks{};
//user_callbacks.InterpreterFallback = &InterpreterFallback;
//user_callbacks.user_arg = static_cast<void*>(interpeter_state.get());
user_callbacks.InterpreterFallback = &InterpreterFallback;
user_callbacks.user_arg = static_cast<void*>(this_);
user_callbacks.CallSVC = &SVC::CallSVC;
user_callbacks.memory.IsReadOnlyMemory = &IsReadOnlyMemory;
user_callbacks.memory.ReadCode = &MemoryRead32;
@ -90,13 +71,13 @@ static Dynarmic::UserCallbacks GetUserCallbacks(
user_callbacks.memory.Write32 = &MemoryWrite32;
user_callbacks.memory.Write64 = &MemoryWrite64;
//user_callbacks.page_table = Memory::GetCurrentPageTablePointers();
user_callbacks.coprocessors[15] = std::make_shared<DynarmicCP15>(interpeter_state);
return user_callbacks;
}
ARM_Dynarmic::ARM_Dynarmic(PrivilegeMode initial_mode) {
interpreter_state = std::make_shared<ARMul_State>(initial_mode);
jit = std::make_unique<Dynarmic::Jit>(GetUserCallbacks(interpreter_state), Dynarmic::Arch::ARM64);
}
void ARM_Dynarmic::MapBackingMemory(VAddr address, size_t size, u8* memory, Kernel::VMAPermission perms) {
}
void ARM_Dynarmic::SetPC(u64 pc) {
@ -115,30 +96,26 @@ void ARM_Dynarmic::SetReg(int index, u64 value) {
jit->Regs64()[index] = value;
}
const u128& ARM_Dynarmic::GetExtReg(int index) const {
return jit->ExtRegs64()[index];
}
void ARM_Dynarmic::SetExtReg(int index, u128& value) {
jit->ExtRegs64()[index] = value;
}
u32 ARM_Dynarmic::GetVFPReg(int index) const {
return jit->ExtRegs()[index];
return {};
}
void ARM_Dynarmic::SetVFPReg(int index, u32 value) {
jit->ExtRegs()[index] = value;
}
u32 ARM_Dynarmic::GetVFPSystemReg(VFPSystemRegister reg) const {
if (reg == VFP_FPSCR) {
return jit->Fpscr();
}
// Dynarmic does not implement and/or expose other VFP registers, fallback to interpreter state
return interpreter_state->VFP[reg];
return {};
}
void ARM_Dynarmic::SetVFPSystemReg(VFPSystemRegister reg, u32 value) {
if (reg == VFP_FPSCR) {
jit->SetFpscr(value);
}
// Dynarmic does not implement and/or expose other VFP registers, fallback to interpreter state
interpreter_state->VFP[reg] = value;
}
u32 ARM_Dynarmic::GetCPSR() const {
@ -150,11 +127,10 @@ void ARM_Dynarmic::SetCPSR(u32 cpsr) {
}
u32 ARM_Dynarmic::GetCP15Register(CP15Register reg) {
return interpreter_state->CP15[reg];
return {};
}
void ARM_Dynarmic::SetCP15Register(CP15Register reg, u32 value) {
interpreter_state->CP15[reg] = value;
}
VAddr ARM_Dynarmic::GetTlsAddress() const {
@ -165,51 +141,39 @@ void ARM_Dynarmic::SetTlsAddress(VAddr address) {
jit->TlsAddr() = address;
}
void ARM_Dynarmic::AddTicks(u64 ticks) {
down_count -= ticks;
if (down_count < 0) {
CoreTiming::Advance();
}
}
MICROPROFILE_DEFINE(ARM_Jit, "ARM JIT", "ARM JIT", MP_RGB(255, 64, 64));
void ARM_Dynarmic::ExecuteInstructions(int num_instructions) {
ASSERT(Memory::GetCurrentPageTable() == current_page_table);
MICROPROFILE_SCOPE(ARM_Jit);
unsigned ticks_executed = jit->Run(1 /*static_cast<unsigned>(num_instructions)*/);
std::size_t ticks_executed = jit->Run(static_cast<unsigned>(num_instructions));
AddTicks(ticks_executed);
CoreTiming::AddTicks(ticks_executed);
}
void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
memcpy(ctx.cpu_registers, jit->Regs64().data(), sizeof(ctx.cpu_registers));
//memcpy(ctx.fpu_registers, jit->ExtRegs().data(), sizeof(ctx.fpu_registers));
memcpy(ctx.fpu_registers, jit->ExtRegs64().data(), sizeof(ctx.fpu_registers));
ctx.lr = jit->Regs64()[30];
ctx.sp = jit->Regs64()[31];
ctx.pc = jit->Regs64()[32];
ctx.cpsr = jit->Cpsr();
ctx.fpscr = jit->Fpscr();
ctx.fpexc = interpreter_state->VFP[VFP_FPEXC];
// TODO(bunnei): Fix once we have proper support for tpidrro_el0, etc. in the JIT
ctx.tls_address = jit->TlsAddr();
}
void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
memcpy(jit->Regs64().data(), ctx.cpu_registers, sizeof(ctx.cpu_registers));
//memcpy(jit->ExtRegs().data(), ctx.fpu_registers, sizeof(ctx.fpu_registers));
memcpy(jit->ExtRegs64().data(), ctx.fpu_registers, sizeof(ctx.fpu_registers));
jit->Regs64()[30] = ctx.lr;
jit->Regs64()[31] = ctx.sp;
jit->Regs64()[32] = ctx.pc;
jit->Cpsr() = ctx.cpsr;
jit->SetFpscr(ctx.fpscr);
interpreter_state->VFP[VFP_FPEXC] = ctx.fpexc;
// TODO(bunnei): Fix once we have proper support for tpidrro_el0, etc. in the JIT
jit->TlsAddr() = ctx.tls_address;
}
@ -223,3 +187,16 @@ void ARM_Dynarmic::PrepareReschedule() {
void ARM_Dynarmic::ClearInstructionCache() {
jit->ClearCache();
}
void ARM_Dynarmic::PageTableChanged() {
current_page_table = Memory::GetCurrentPageTable();
auto iter = jits.find(current_page_table);
if (iter != jits.end()) {
jit = iter->second.get();
return;
}
jit = new Dynarmic::Jit(GetUserCallbacks(this), Dynarmic::Arch::ARM64);
jits.emplace(current_page_table, std::unique_ptr<Dynarmic::Jit>(jit));
}

17
src/core/arm/dynarmic/arm_dynarmic.h
View file

@ -4,20 +4,29 @@
#pragma once
#include <map>
#include <memory>
#include <dynarmic/dynarmic.h>
#include "common/common_types.h"
#include "core/arm/arm_interface.h"
#include "core/arm/skyeye_common/armstate.h"
namespace Memory {
struct PageTable;
} // namespace Memory
class ARM_Dynarmic final : public ARM_Interface {
public:
ARM_Dynarmic(PrivilegeMode initial_mode);
void MapBackingMemory(VAddr address, size_t size, u8* memory, Kernel::VMAPermission perms) override;
void SetPC(u64 pc) override;
u64 GetPC() const override;
u64 GetReg(int index) const override;
void SetReg(int index, u64 value) override;
const u128& GetExtReg(int index) const override;
void SetExtReg(int index, u128& value) override;
u32 GetVFPReg(int index) const override;
void SetVFPReg(int index, u32 value) override;
u32 GetVFPSystemReg(VFPSystemRegister reg) const override;
@ -29,8 +38,6 @@ public:
VAddr GetTlsAddress() const override;
void SetTlsAddress(VAddr address) override;
void AddTicks(u64 ticks) override;
void SaveContext(ThreadContext& ctx) override;
void LoadContext(const ThreadContext& ctx) override;
@ -38,8 +45,10 @@ public:
void ExecuteInstructions(int num_instructions) override;
void ClearInstructionCache() override;
void PageTableChanged() override;
private:
std::unique_ptr<Dynarmic::Jit> jit;
std::shared_ptr<ARMul_State> interpreter_state;
Dynarmic::Jit* jit = nullptr;
Memory::PageTable* current_page_table = nullptr;
std::map<Memory::PageTable*, std::unique_ptr<Dynarmic::Jit>> jits;
};

19
src/core/arm/dyncom/arm_dyncom.cpp
View file

@ -29,6 +29,10 @@ void ARM_DynCom::SetPC(u64 pc) {
state->Reg[15] = pc;
}
void ARM_DynCom::PageTableChanged() {
ClearInstructionCache();
}
u64 ARM_DynCom::GetPC() const {
return state->Reg[15];
}
@ -41,6 +45,13 @@ void ARM_DynCom::SetReg(int index, u64 value) {
state->Reg[index] = value;
}
const u128& ARM_DynCom::GetExtReg(int index) const {
return {};
}
void ARM_DynCom::SetExtReg(int index, u128& value) {
}
u32 ARM_DynCom::GetVFPReg(int index) const {
return state->ExtReg[index];
}
@ -80,12 +91,6 @@ VAddr ARM_DynCom::GetTlsAddress() const {
void ARM_DynCom::SetTlsAddress(VAddr /*address*/) {
}
void ARM_DynCom::AddTicks(u64 ticks) {
down_count -= ticks;
if (down_count < 0)
CoreTiming::Advance();
}
void ARM_DynCom::ExecuteInstructions(int num_instructions) {
state->NumInstrsToExecute = num_instructions;
@ -93,7 +98,7 @@ void ARM_DynCom::ExecuteInstructions(int num_instructions) {
// executing one instruction at a time. Otherwise, if a block is being executed, more
// instructions may actually be executed than specified.
unsigned ticks_executed = InterpreterMainLoop(state.get());
AddTicks(ticks_executed);
CoreTiming::AddTicks(ticks_executed);
}
void ARM_DynCom::SaveContext(ThreadContext& ctx) {

5
src/core/arm/dyncom/arm_dyncom.h
View file

@ -16,11 +16,14 @@ public:
~ARM_DynCom();
void ClearInstructionCache() override;
void PageTableChanged() override;
void SetPC(u64 pc) override;
u64 GetPC() const override;
u64 GetReg(int index) const override;
void SetReg(int index, u64 value) override;
const u128& GetExtReg(int index) const override;
void SetExtReg(int index, u128& value) override;
u32 GetVFPReg(int index) const override;
void SetVFPReg(int index, u32 value) override;
u32 GetVFPSystemReg(VFPSystemRegister reg) const override;
@ -32,8 +35,6 @@ public:
VAddr GetTlsAddress() const override;
void SetTlsAddress(VAddr address) override;
void AddTicks(u64 ticks) override;
void SaveContext(ThreadContext& ctx) override;
void LoadContext(const ThreadContext& ctx) override;

8
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
View file

@ -759,7 +759,7 @@ static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_ins
ThumbDecodeStatus ret = TranslateThumbInstruction(addr, inst, arm_inst, inst_size);
if (ret == ThumbDecodeStatus::BRANCH) {
int inst_index;
int table_length = arm_instruction_trans_len;
int table_length = static_cast<int>(arm_instruction_trans_len);
u32 tinstr = GetThumbInstruction(inst, addr);
switch ((tinstr & 0xF800) >> 11) {
@ -838,7 +838,7 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons
return inst_size;
}
static int InterpreterTranslateBlock(ARMul_State* cpu, int& bb_start, u32 addr) {
static int InterpreterTranslateBlock(ARMul_State* cpu, std::size_t& bb_start, u32 addr) {
MICROPROFILE_SCOPE(DynCom_Decode);
// Decode instruction, get index
@ -871,7 +871,7 @@ static int InterpreterTranslateBlock(ARMul_State* cpu, int& bb_start, u32 addr)
return KEEP_GOING;
}
static int InterpreterTranslateSingle(ARMul_State* cpu, int& bb_start, u32 addr) {
static int InterpreterTranslateSingle(ARMul_State* cpu, std::size_t& bb_start, u32 addr) {
MICROPROFILE_SCOPE(DynCom_Decode);
ARM_INST_PTR inst_base = nullptr;
@ -1620,7 +1620,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
unsigned int addr;
unsigned int num_instrs = 0;
int ptr;
std::size_t ptr;
LOAD_NZCVT;
DISPATCH : {

2
src/core/arm/skyeye_common/armstate.h
View file

@ -230,7 +230,7 @@ public:
// TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per
// process for our purposes), not per ARMul_State (which tracks CPU core state).
std::unordered_map<u32, int> instruction_cache;
std::unordered_map<u32, std::size_t> instruction_cache;
private:
void ResetMPCoreCP15Registers();