Move CP15 enum definitions into their own enum.

Also gets rid of preprocessor mumbo-jumbo

src/core/arm/skyeye_common/arm_regformat.h

@@ -51,17 +51,23 @@ enum {
     EXCLUSIVE_STATE,
     EXCLUSIVE_RESULT,
 
+    // VFP registers
+    VFP_BASE,
+    VFP_FPSID = VFP_BASE,
+    VFP_FPSCR,
+    VFP_FPEXC,
+
+    MAX_REG_NUM,
+};
+
+enum CP15Register {
     // c0 - Information registers
-    CP15_BASE,
-    CP15_C0 = CP15_BASE,
-    CP15_C0_C0 = CP15_C0,
-    CP15_MAIN_ID = CP15_C0_C0,
+    CP15_MAIN_ID,
     CP15_CACHE_TYPE,
     CP15_TCM_STATUS,
     CP15_TLB_TYPE,
     CP15_CPU_ID,
-    CP15_C0_C1,
-    CP15_PROCESSOR_FEATURE_0 = CP15_C0_C1,
+    CP15_PROCESSOR_FEATURE_0,
     CP15_PROCESSOR_FEATURE_1,
     CP15_DEBUG_FEATURE_0,
     CP15_AUXILIARY_FEATURE_0,
@@ -69,24 +75,19 @@ enum {
     CP15_MEMORY_MODEL_FEATURE_1,
     CP15_MEMORY_MODEL_FEATURE_2,
     CP15_MEMORY_MODEL_FEATURE_3,
-    CP15_C0_C2,
-    CP15_ISA_FEATURE_0 = CP15_C0_C2,
+    CP15_ISA_FEATURE_0,
     CP15_ISA_FEATURE_1,
     CP15_ISA_FEATURE_2,
     CP15_ISA_FEATURE_3,
     CP15_ISA_FEATURE_4,
 
     // c1 - Control registers
-    CP15_C1_C0,
-    CP15_CONTROL = CP15_C1_C0,
+    CP15_CONTROL,
     CP15_AUXILIARY_CONTROL,
     CP15_COPROCESSOR_ACCESS_CONTROL,
 
     // c2 - Translation table registers
-    CP15_C2,
-    CP15_C2_C0 = CP15_C2,
-    CP15_TRANSLATION_BASE = CP15_C2_C0,
-    CP15_TRANSLATION_BASE_TABLE_0 = CP15_TRANSLATION_BASE,
+    CP15_TRANSLATION_BASE_TABLE_0,
     CP15_TRANSLATION_BASE_TABLE_1,
     CP15_TRANSLATION_BASE_CONTROL,
     CP15_DOMAIN_ACCESS_CONTROL,
@@ -171,14 +172,9 @@ enum {
     CP15_TLB_FAULT_ADDR,
     CP15_TLB_FAULT_STATUS,
 
-    // VFP registers
-    VFP_BASE,
-    VFP_FPSID = VFP_BASE,
-    VFP_FPSCR,
-    VFP_FPEXC,
-
-    MAX_REG_NUM,
+    // Not an actual register.
+    // All registers should be defined above this.
+    CP15_REGISTER_COUNT,
 };
 
-#define CP15(idx)       (idx - CP15_BASE)
 #define VFP_OFFSET(x)   (x - VFP_BASE)

src/core/arm/skyeye_common/armdefs.h

@@ -91,7 +91,7 @@ struct ARMul_State
     ARMword exclusive_tag;      // The address for which the local monitor is in exclusive access mode
     ARMword exclusive_state;
     ARMword exclusive_result;
-    ARMword CP15[VFP_BASE - CP15_BASE];
+    ARMword CP15[CP15_REGISTER_COUNT];
     ARMword VFP[3]; // FPSID, FPSCR, and FPEXC
     // VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
     // VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),