Mirrors/yuzu
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

shader: Address Feedback

Browse source
This commit is contained in:
FernandoS27 2021-04-03 01:48:39 +02:00 • committed by ameerj
parent 45d547af11
commit baec84247f
16 changed files with 60 additions and 211 deletions
Download patch file Download diff file Expand all files Collapse all files

49
src/shader_recompiler/frontend/ir/ir_emitter.cpp
View file

@ -82,8 +82,17 @@ void IREmitter::SelectionMerge(Block* merge_block) {
Inst(Opcode::SelectionMerge, merge_block);
}
void IREmitter::MemoryBarrier(BarrierInstInfo info) {
Inst(Opcode::MemoryBarrier, Flags{info});
void IREmitter::MemoryBarrier(MemoryScope scope) {
switch (scope) {
case MemoryScope::Workgroup:
Inst(Opcode::MemoryBarrierWorkgroupLevel);
case MemoryScope::Device:
Inst(Opcode::MemoryBarrierDeviceLevel);
case MemoryScope::System:
Inst(Opcode::MemoryBarrierSystemLevel);
default:
throw InvalidArgument("Invalid memory scope {}", scope);
}
}
void IREmitter::Return() {
@ -202,38 +211,6 @@ void IREmitter::SetOFlag(const U1& value) {
Inst(Opcode::SetOFlag, value);
}
U1 IREmitter::GetFCSMFlag() {
return Inst<U1>(Opcode::GetFCSMFlag);
}
U1 IREmitter::GetTAFlag() {
return Inst<U1>(Opcode::GetTAFlag);
}
U1 IREmitter::GetTRFlag() {
return Inst<U1>(Opcode::GetTRFlag);
}
U1 IREmitter::GetMXFlag() {
return Inst<U1>(Opcode::GetMXFlag);
}
void IREmitter::SetFCSMFlag(const U1& value) {
Inst(Opcode::SetFCSMFlag, value);
}
void IREmitter::SetTAFlag(const U1& value) {
Inst(Opcode::SetTAFlag, value);
}
void IREmitter::SetTRFlag(const U1& value) {
Inst(Opcode::SetTRFlag, value);
}
void IREmitter::SetMXFlag(const U1& value) {
Inst(Opcode::SetMXFlag, value);
}
static U1 GetFlowTest(IREmitter& ir, FlowTest flow_test) {
switch (flow_test) {
case FlowTest::F:
@ -292,9 +269,9 @@ static U1 GetFlowTest(IREmitter& ir, FlowTest flow_test) {
return ir.LogicalOr(ir.GetSFlag(), ir.GetZFlag());
case FlowTest::RGT:
return ir.LogicalAnd(ir.LogicalNot(ir.GetSFlag()), ir.LogicalNot(ir.GetZFlag()));
case FlowTest::FCSM_TR:
return ir.LogicalAnd(ir.GetFCSMFlag(), ir.GetTRFlag());
// LOG_WARNING(ShaderDecompiler, "FCSM_TR CC State (Stubbed)");
return ir.Imm1(false);
case FlowTest::CSM_TA:
case FlowTest::CSM_TR:
case FlowTest::CSM_MX:

12
src/shader_recompiler/frontend/ir/ir_emitter.h
View file

@ -70,16 +70,6 @@ public:
void SetCFlag(const U1& value);
void SetOFlag(const U1& value);
[[nodiscard]] U1 GetFCSMFlag();
[[nodiscard]] U1 GetTAFlag();
[[nodiscard]] U1 GetTRFlag();
[[nodiscard]] U1 GetMXFlag();
void SetFCSMFlag(const U1& value);
void SetTAFlag(const U1& value);
void SetTRFlag(const U1& value);
void SetMXFlag(const U1& value);
[[nodiscard]] U1 Condition(IR::Condition cond);
[[nodiscard]] U1 GetFlowTestResult(FlowTest test);
@ -138,7 +128,7 @@ public:
[[nodiscard]] Value Select(const U1& condition, const Value& true_value,
const Value& false_value);
[[nodiscard]] void MemoryBarrier(BarrierInstInfo info);
[[nodiscard]] void MemoryBarrier(MemoryScope scope);
template <typename Dest, typename Source>
[[nodiscard]] Dest BitCast(const Source& value);

13
src/shader_recompiler/frontend/ir/modifiers.h
View file

@ -25,13 +25,7 @@ enum class FpRounding : u8 {
RZ, // Round towards zero
};
enum class MemoryScope : u32 {
DontCare,
Warp,
Workgroup,
Device,
System
};
enum class MemoryScope : u32 { DontCare, Warp, Workgroup, Device, System };
struct FpControl {
bool no_contraction{false};
@ -40,11 +34,6 @@ struct FpControl {
};
static_assert(sizeof(FpControl) <= sizeof(u32));
union BarrierInstInfo {
u32 raw;
BitField<0, 3, MemoryScope> scope;
};
union TextureInstInfo {
u32 raw;
BitField<0, 8, TextureType> type;

12
src/shader_recompiler/frontend/ir/opcodes.inc
View file

@ -17,7 +17,9 @@ OPCODE(Unreachable, Void,
OPCODE(DemoteToHelperInvocation, Void, Label, )
// Barriers
OPCODE(MemoryBarrier, Void, )
OPCODE(MemoryBarrierWorkgroupLevel, Void, )
OPCODE(MemoryBarrierDeviceLevel, Void, )
OPCODE(MemoryBarrierSystemLevel, Void, )
// Special operations
OPCODE(Prologue, Void, )
@ -49,18 +51,10 @@ OPCODE(GetZFlag, U1, Void
OPCODE(GetSFlag, U1, Void, )
OPCODE(GetCFlag, U1, Void, )
OPCODE(GetOFlag, U1, Void, )
OPCODE(GetFCSMFlag, U1, Void, )
OPCODE(GetTAFlag, U1, Void, )
OPCODE(GetTRFlag, U1, Void, )
OPCODE(GetMXFlag, U1, Void, )
OPCODE(SetZFlag, Void, U1, )
OPCODE(SetSFlag, Void, U1, )
OPCODE(SetCFlag, Void, U1, )
OPCODE(SetOFlag, Void, U1, )
OPCODE(SetFCSMFlag, Void, U1, )
OPCODE(SetTAFlag, Void, U1, )
OPCODE(SetTRFlag, Void, U1, )
OPCODE(SetMXFlag, Void, U1, )
OPCODE(WorkgroupId, U32x3, )
OPCODE(LocalInvocationId, U32x3, )
OPCODE(LaneId, U32, )

12
src/shader_recompiler/frontend/maxwell/translate/impl/barrier_operations.cpp
View file

@ -5,8 +5,8 @@
#include "common/bit_field.h"
#include "common/common_types.h"
#include "shader_recompiler/frontend/ir/modifiers.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
#include "shader_recompiler/frontend/maxwell/opcodes.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
namespace Shader::Maxwell {
namespace {
@ -21,28 +21,24 @@ enum class LocalScope : u64 {
IR::MemoryScope LocalScopeToMemoryScope(LocalScope scope) {
switch (scope) {
case LocalScope::CTG:
return IR::MemoryScope::Warp;
return IR::MemoryScope::Workgroup;
case LocalScope::GL:
return IR::MemoryScope::Device;
case LocalScope::SYS:
return IR::MemoryScope::System;
case LocalScope::VC:
return IR::MemoryScope::Workgroup; // or should be device?
default:
throw NotImplementedException("Unimplemented Local Scope {}", scope);
}
}
} // namespace
} // Anonymous namespace
void TranslatorVisitor::MEMBAR(u64 inst) {
union {
u64 raw;
BitField<8, 2, LocalScope> scope;
} membar{inst};
IR::BarrierInstInfo info{};
info.scope.Assign(LocalScopeToMemoryScope(membar.scope));
ir.MemoryBarrier(info);
ir.MemoryBarrier(LocalScopeToMemoryScope(membar.scope));
}
void TranslatorVisitor::DEPBAR() {

2
src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp
View file

@ -96,8 +96,10 @@ enum class SpecialRegister : u64 {
case SpecialRegister::SR_CTAID_Z:
return ir.WorkgroupIdZ();
case SpecialRegister::SR_WSCALEFACTOR_XY:
// LOG_WARNING(ShaderDecompiler, "SR_WSCALEFACTOR_XY (Stubbed)");
return ir.Imm32(Common::BitCast<u32>(1.0f));
case SpecialRegister::SR_WSCALEFACTOR_Z:
// LOG_WARNING(ShaderDecompiler, "SR_WSCALEFACTOR_Z (Stubbed)");
return ir.Imm32(Common::BitCast<u32>(1.0f));
case SpecialRegister::SR_LANEID:
return ir.LaneId();

5
src/shader_recompiler/frontend/maxwell/translate/impl/vote.cpp
View file

@ -50,10 +50,7 @@ void TranslatorVisitor::VOTE(u64 insn) {
}
void TranslatorVisitor::VOTE_vtg(u64) {
// LOG_WARNING("VOTE.VTG: Stubbed!");
auto imm = ir.Imm1(false);
ir.SetFCSMFlag(imm);
ir.SetTRFlag(imm);
// LOG_WARNING(ShaderDecompiler, "VOTE.VTG: Stubbed!");
}
} // namespace Shader::Maxwell