glasm: Catch more register leaks
Add support for null registers. These are used when an instruction has no usages. This comes handy when an instruction is only used for its CC value, with the caveat of having to invalidate all pseudo-instructions before defining the instruction itself in the register allocator. This commits changes this. Workaround a bug on Nvidia's condition codes conditional execution using branches.
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9fbfe7d676
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ca05a13c62
8 changed files with 114 additions and 41 deletions
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@ -22,11 +22,19 @@ Register RegAlloc::LongDefine(IR::Inst& inst) {
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}
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Value RegAlloc::Peek(const IR::Value& value) {
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return value.IsImmediate() ? MakeImm(value) : PeekInst(*value.InstRecursive());
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if (value.IsImmediate()) {
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return MakeImm(value);
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} else {
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return PeekInst(*value.Inst());
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}
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}
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Value RegAlloc::Consume(const IR::Value& value) {
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return value.IsImmediate() ? MakeImm(value) : ConsumeInst(*value.InstRecursive());
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if (value.IsImmediate()) {
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return MakeImm(value);
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} else {
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return ConsumeInst(*value.Inst());
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}
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}
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void RegAlloc::Unref(IR::Inst& inst) {
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@ -88,7 +96,14 @@ Value RegAlloc::MakeImm(const IR::Value& value) {
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}
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Register RegAlloc::Define(IR::Inst& inst, bool is_long) {
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inst.SetDefinition<Id>(Alloc(is_long));
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if (inst.HasUses()) {
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inst.SetDefinition<Id>(Alloc(is_long));
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} else {
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Id id{};
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id.is_long.Assign(is_long ? 1 : 0);
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id.is_null.Assign(1);
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inst.SetDefinition<Id>(id);
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}
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return Register{PeekInst(inst)};
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}
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@ -115,10 +130,12 @@ Id RegAlloc::Alloc(bool is_long) {
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num_regs = std::max(num_regs, reg + 1);
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use[reg] = true;
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Id ret{};
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ret.index.Assign(static_cast<u32>(reg));
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ret.is_valid.Assign(1);
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ret.is_long.Assign(is_long ? 1 : 0);
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ret.is_spill.Assign(0);
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ret.is_condition_code.Assign(0);
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ret.is_null.Assign(0);
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ret.index.Assign(static_cast<u32>(reg));
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return ret;
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}
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}
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@ -126,6 +143,9 @@ Id RegAlloc::Alloc(bool is_long) {
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}
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void RegAlloc::Free(Id id) {
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if (id.is_valid == 0) {
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throw LogicError("Freeing invalid register");
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}
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if (id.is_spill != 0) {
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throw NotImplementedException("Free spill");
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}
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