Mirrors/yuzu
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

shader: Implement SHR

Browse source
This commit is contained in:
ameerj 2021-02-25 00:46:40 -05:00
parent 8810c88b7e
commit cc55d28949
8 changed files with 80 additions and 18 deletions
Download patch file Download diff file Expand all files Collapse all files

12
src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
View file

@ -70,12 +70,12 @@ Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
}
void EmitShiftRightLogical32(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b) {
return ctx.OpShiftRightLogical(ctx.U32[1], a, b);
}
void EmitShiftRightArithmetic32(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b) {
return ctx.OpShiftRightArithmetic(ctx.U32[1], a, b);
}
Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) {
@ -102,6 +102,10 @@ Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) {
return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count);
}
Id EmitBitReverse32(EmitContext& ctx, Id value) {
return ctx.OpBitReverse(ctx.U32[1], value);
}
Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
return ctx.OpSLessThan(ctx.U1, lhs, rhs);
}