Merge pull request #2753 from FernandoS27/float-convert
Shader_Ir: Implement F16 Variants of F2F, F2I, I2F.
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commit
cedc1aab4a
5 changed files with 75 additions and 18 deletions
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@ -57,7 +57,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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case OpCode::Id::I2F_R:
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case OpCode::Id::I2F_C:
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case OpCode::Id::I2F_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
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UNIMPLEMENTED_IF(instr.conversion.selector);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in I2F is not implemented");
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@ -82,14 +82,19 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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value = GetOperandAbsNegFloat(value, false, instr.conversion.negate_a);
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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if (instr.conversion.dst_size == Register::Size::Short) {
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value = Operation(OperationCode::HCastFloat, PRECISE, value);
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}
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::F2F_R:
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case OpCode::Id::F2F_C:
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case OpCode::Id::F2F_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.f2f.dst_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.conversion.f2f.src_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
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UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in F2F is not implemented");
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@ -107,6 +112,11 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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}
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}();
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if (instr.conversion.src_size == Register::Size::Short) {
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// TODO: figure where extract is sey in the encoding
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value = Operation(OperationCode::FCastHalf0, PRECISE, value);
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}
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value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
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value = [&]() {
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@ -124,19 +134,24 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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default:
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UNIMPLEMENTED_MSG("Unimplemented F2F rounding mode {}",
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static_cast<u32>(instr.conversion.f2f.rounding.Value()));
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return Immediate(0);
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return value;
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}
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}();
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value = GetSaturatedFloat(value, instr.alu.saturate_d);
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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if (instr.conversion.dst_size == Register::Size::Short) {
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value = Operation(OperationCode::HCastFloat, PRECISE, value);
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}
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::F2I_R:
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case OpCode::Id::F2I_C:
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case OpCode::Id::F2I_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.src_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in F2I is not implemented");
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Node value = [&]() {
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@ -153,6 +168,11 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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}
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}();
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if (instr.conversion.src_size == Register::Size::Short) {
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// TODO: figure where extract is sey in the encoding
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value = Operation(OperationCode::FCastHalf0, PRECISE, value);
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}
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value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
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value = [&]() {
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