glasm: Rework control flow introducing a syntax list
This commit regresses VertexA shaders, their transformation pass has to be adapted to the new control flow.
This commit is contained in:
parent
7ff5851608
commit
d54d7de40e
33 changed files with 437 additions and 505 deletions
|
@ -117,8 +117,6 @@ auto Arg(EmitContext& ctx, const IR::Value& arg) {
|
|||
return Identity<const IR::Value&>{arg};
|
||||
} else if constexpr (std::is_same_v<ArgType, u32>) {
|
||||
return Identity{arg.U32()};
|
||||
} else if constexpr (std::is_same_v<ArgType, IR::Block*>) {
|
||||
return Identity{arg.Label()};
|
||||
} else if constexpr (std::is_same_v<ArgType, IR::Attribute>) {
|
||||
return Identity{arg.Attribute()};
|
||||
} else if constexpr (std::is_same_v<ArgType, IR::Patch>) {
|
||||
|
@ -177,6 +175,39 @@ void EmitInst(EmitContext& ctx, IR::Inst* inst) {
|
|||
throw LogicError("Invalid opcode {}", inst->GetOpcode());
|
||||
}
|
||||
|
||||
void EmitCode(EmitContext& ctx, const IR::Program& program) {
|
||||
const auto eval{
|
||||
[&](const IR::U1& cond) { return ScalarS32{ctx.reg_alloc.Consume(IR::Value{cond})}; }};
|
||||
for (const IR::AbstractSyntaxNode& node : program.syntax_list) {
|
||||
switch (node.type) {
|
||||
case IR::AbstractSyntaxNode::Type::Block:
|
||||
for (IR::Inst& inst : node.block->Instructions()) {
|
||||
EmitInst(ctx, &inst);
|
||||
}
|
||||
break;
|
||||
case IR::AbstractSyntaxNode::Type::If:
|
||||
ctx.Add("MOV.S.CC RC,{};IF NE.x;", eval(node.if_node.cond));
|
||||
break;
|
||||
case IR::AbstractSyntaxNode::Type::EndIf:
|
||||
ctx.Add("ENDIF;");
|
||||
break;
|
||||
case IR::AbstractSyntaxNode::Type::Loop:
|
||||
ctx.Add("REP;");
|
||||
break;
|
||||
case IR::AbstractSyntaxNode::Type::Repeat:
|
||||
ctx.Add("MOV.S.CC RC,{};BRK NE.x;ENDREP;", eval(node.repeat.cond));
|
||||
break;
|
||||
case IR::AbstractSyntaxNode::Type::Break:
|
||||
ctx.Add("MOV.S.CC RC,{};BRK NE.x;", eval(node.repeat.cond));
|
||||
break;
|
||||
case IR::AbstractSyntaxNode::Type::Return:
|
||||
case IR::AbstractSyntaxNode::Type::Unreachable:
|
||||
ctx.Add("RET;");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void SetupOptions(std::string& header, Info info) {
|
||||
if (info.uses_int64_bit_atomics) {
|
||||
header += "OPTION NV_shader_atomic_int64;";
|
||||
|
@ -201,11 +232,7 @@ void SetupOptions(std::string& header, Info info) {
|
|||
|
||||
std::string EmitGLASM(const Profile&, IR::Program& program, Bindings&) {
|
||||
EmitContext ctx{program};
|
||||
for (IR::Block* const block : program.blocks) {
|
||||
for (IR::Inst& inst : block->Instructions()) {
|
||||
EmitInst(ctx, &inst);
|
||||
}
|
||||
}
|
||||
EmitCode(ctx, program);
|
||||
std::string header = "!!NVcp5.0\n"
|
||||
"OPTION NV_internal;";
|
||||
SetupOptions(header, program.info);
|
||||
|
|
|
@ -22,13 +22,8 @@ class EmitContext;
|
|||
void EmitPhi(EmitContext& ctx, IR::Inst& inst);
|
||||
void EmitVoid(EmitContext& ctx);
|
||||
void EmitIdentity(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
|
||||
void EmitBranch(EmitContext& ctx);
|
||||
void EmitBranchConditional(EmitContext& ctx);
|
||||
void EmitLoopMerge(EmitContext& ctx);
|
||||
void EmitSelectionMerge(EmitContext& ctx);
|
||||
void EmitReturn(EmitContext& ctx);
|
||||
void EmitBranchConditionRef(EmitContext&);
|
||||
void EmitJoin(EmitContext& ctx);
|
||||
void EmitUnreachable(EmitContext& ctx);
|
||||
void EmitDemoteToHelperInvocation(EmitContext& ctx);
|
||||
void EmitBarrier(EmitContext& ctx);
|
||||
void EmitWorkgroupMemoryBarrier(EmitContext& ctx);
|
||||
|
|
|
@ -91,7 +91,8 @@ void EmitBitFieldInsert(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, Scalar
|
|||
if (count.type != Type::Register && offset.type != Type::Register) {
|
||||
ctx.Add("BFI.S {},{{{},{},0,0}},{},{};", ret, count, offset, insert, base);
|
||||
} else {
|
||||
ctx.Add("MOV.S RC.x,{};MOV.U RC.y,{};"
|
||||
ctx.Add("MOV.S RC.x,{};"
|
||||
"MOV.S RC.y,{};"
|
||||
"BFI.S {},RC,{},{};",
|
||||
count, offset, ret, insert, base);
|
||||
}
|
||||
|
@ -103,7 +104,8 @@ void EmitBitFieldSExtract(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, Scal
|
|||
if (count.type != Type::Register && offset.type != Type::Register) {
|
||||
ctx.Add("BFE.S {},{{{},{},0,0}},{};", ret, count, offset, base);
|
||||
} else {
|
||||
ctx.Add("MOV.S RC.x,{};MOV.U RC.y,{};"
|
||||
ctx.Add("MOV.S RC.x,{};"
|
||||
"MOV.S RC.y,{};"
|
||||
"BFE.S {},RC,{};",
|
||||
count, offset, ret, base);
|
||||
}
|
||||
|
@ -115,7 +117,8 @@ void EmitBitFieldUExtract(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, Scal
|
|||
if (count.type != Type::Register && offset.type != Type::Register) {
|
||||
ctx.Add("BFE.U {},{{{},{},0,0}},{};", ret, count, offset, base);
|
||||
} else {
|
||||
ctx.Add("MOV.U RC.x,{};MOV.U RC.y,{};"
|
||||
ctx.Add("MOV.U RC.x,{};"
|
||||
"MOV.U RC.y,{};"
|
||||
"BFE.U {},RC,{};",
|
||||
count, offset, ret, base);
|
||||
}
|
||||
|
|
|
@ -23,34 +23,12 @@ void EmitPhi(EmitContext& ctx, IR::Inst& inst) {
|
|||
|
||||
void EmitVoid(EmitContext&) {}
|
||||
|
||||
void EmitBranch(EmitContext& ctx) {
|
||||
NotImplemented();
|
||||
}
|
||||
|
||||
void EmitBranchConditional(EmitContext& ctx) {
|
||||
NotImplemented();
|
||||
}
|
||||
|
||||
void EmitLoopMerge(EmitContext& ctx) {
|
||||
NotImplemented();
|
||||
}
|
||||
|
||||
void EmitSelectionMerge(EmitContext& ctx) {
|
||||
NotImplemented();
|
||||
}
|
||||
|
||||
void EmitReturn(EmitContext& ctx) {
|
||||
ctx.Add("RET;");
|
||||
}
|
||||
void EmitBranchConditionRef(EmitContext&) {}
|
||||
|
||||
void EmitJoin(EmitContext& ctx) {
|
||||
NotImplemented();
|
||||
}
|
||||
|
||||
void EmitUnreachable(EmitContext& ctx) {
|
||||
NotImplemented();
|
||||
}
|
||||
|
||||
void EmitDemoteToHelperInvocation(EmitContext& ctx) {
|
||||
NotImplemented();
|
||||
}
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue