video_core: Implement IR based geometry shaders
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a1b845b651
commit
e1fea1e0c5
4 changed files with 102 additions and 10 deletions
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@ -12,6 +12,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::ConditionCode;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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@ -140,6 +141,30 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::OUT_R: {
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UNIMPLEMENTED_IF_MSG(instr.gpr20.Value() != Register::ZeroIndex,
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"Stream buffer is not supported");
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if (instr.out.emit) {
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// gpr0 is used to store the next address and gpr8 contains the address to emit.
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// Hardware uses pointers here but we just ignore it
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bb.push_back(Operation(OperationCode::EmitVertex));
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SetRegister(bb, instr.gpr0, Immediate(0));
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}
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if (instr.out.cut) {
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bb.push_back(Operation(OperationCode::EndPrimitive));
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}
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break;
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}
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case OpCode::Id::ISBERD: {
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UNIMPLEMENTED_IF(instr.isberd.o != 0);
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UNIMPLEMENTED_IF(instr.isberd.skew != 0);
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UNIMPLEMENTED_IF(instr.isberd.shift != Tegra::Shader::IsberdShift::None);
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UNIMPLEMENTED_IF(instr.isberd.mode != Tegra::Shader::IsberdMode::None);
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LOG_WARNING(HW_GPU, "ISBERD instruction is incomplete");
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SetRegister(bb, instr.gpr0, GetRegister(instr.gpr8));
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break;
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}
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case OpCode::Id::DEPBAR: {
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LOG_WARNING(HW_GPU, "DEPBAR instruction is stubbed");
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break;
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