Mirrors/yuzu
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

shader: FMUL, select, RRO, and MUFU fixes

Browse source
This commit is contained in:
ReinUsesLisp 2021-02-22 22:59:16 -03:00 • committed by ameerj
parent 18a766b362
commit e44752ddc8
18 changed files with 507 additions and 119 deletions
Download patch file Download diff file Expand all files Collapse all files

21
src/shader_recompiler/backend/spirv/emit_spirv_select.cpp
View file

@ -6,20 +6,29 @@
namespace Shader::Backend::SPIRV {
void EmitSelect8(EmitContext&) {
Id EmitSelectU8([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Id cond,
[[maybe_unused]] Id true_value, [[maybe_unused]] Id false_value) {
throw NotImplementedException("SPIR-V Instruction");
}
void EmitSelect16(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
Id EmitSelectU16(EmitContext& ctx, Id cond, Id true_value, Id false_value) {
return ctx.OpSelect(ctx.U16, cond, true_value, false_value);
}
Id EmitSelect32(EmitContext& ctx, Id cond, Id true_value, Id false_value) {
Id EmitSelectU32(EmitContext& ctx, Id cond, Id true_value, Id false_value) {
return ctx.OpSelect(ctx.U32[1], cond, true_value, false_value);
}
void EmitSelect64(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
Id EmitSelectU64(EmitContext& ctx, Id cond, Id true_value, Id false_value) {
return ctx.OpSelect(ctx.U64, cond, true_value, false_value);
}
Id EmitSelectF16(EmitContext& ctx, Id cond, Id true_value, Id false_value) {
return ctx.OpSelect(ctx.F16[1], cond, true_value, false_value);
}
Id EmitSelectF32(EmitContext& ctx, Id cond, Id true_value, Id false_value) {
return ctx.OpSelect(ctx.F32[1], cond, true_value, false_value);
}
} // namespace Shader::Backend::SPIRV