video_core: Return safe values after an assert hits

src/video_core/shader/decode/arithmetic.cpp

@@ -115,6 +115,7 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
             default:
                 UNIMPLEMENTED_MSG("Unhandled MUFU sub op={0:x}",
                                   static_cast<unsigned>(instr.sub_op.Value()));
+                return Immediate(0);
             }
         }();
         value = GetSaturatedFloat(value, instr.alu.saturate_d);

src/video_core/shader/decode/arithmetic_integer_immediate.cpp

@@ -62,6 +62,7 @@ void ShaderIR::WriteLogicOperation(BasicBlock& bb, Register dest, LogicOperation
             return op_b;
         default:
             UNIMPLEMENTED_MSG("Unimplemented logic operation={}", static_cast<u32>(logic_op));
+            return Immediate(0);
         }
     }();
 

src/video_core/shader/decode/bfi.cpp

@@ -24,6 +24,7 @@ u32 ShaderIR::DecodeBfi(BasicBlock& bb, u32 pc) {
             return {GetRegister(instr.gpr39), Immediate(instr.alu.GetSignedImm20_20())};
         default:
             UNREACHABLE();
+            return {Immediate(0), Immediate(0)};
         }
     }();
     const Node insert = GetRegister(instr.gpr8);

src/video_core/shader/decode/conversion.cpp

@@ -96,11 +96,10 @@ u32 ShaderIR::DecodeConversion(BasicBlock& bb, u32 pc) {
                 return Operation(OperationCode::FCeil, PRECISE, value);
             case Tegra::Shader::F2fRoundingOp::Trunc:
                 return Operation(OperationCode::FTrunc, PRECISE, value);
-            default:
-                UNIMPLEMENTED_MSG("Unimplemented F2F rounding mode {}",
-                                  static_cast<u32>(instr.conversion.f2f.rounding.Value()));
-                break;
             }
+            UNIMPLEMENTED_MSG("Unimplemented F2F rounding mode {}",
+                              static_cast<u32>(instr.conversion.f2f.rounding.Value()));
+            return Immediate(0);
         }();
         value = GetSaturatedFloat(value, instr.alu.saturate_d);
 
@@ -135,6 +134,7 @@ u32 ShaderIR::DecodeConversion(BasicBlock& bb, u32 pc) {
             default:
                 UNIMPLEMENTED_MSG("Unimplemented F2I rounding mode {}",
                                   static_cast<u32>(instr.conversion.f2i.rounding.Value()));
+                return Immediate(0);
             }
         }();
         const bool is_signed = instr.conversion.is_output_signed;

src/video_core/shader/decode/ffma.cpp

@@ -42,6 +42,7 @@ u32 ShaderIR::DecodeFfma(BasicBlock& bb, u32 pc) {
             return {GetImmediate19(instr), GetRegister(instr.gpr39)};
         default:
             UNIMPLEMENTED_MSG("Unhandled FFMA instruction: {}", opcode->get().GetName());
+            return {Immediate(0), Immediate(0)};
         }
     }();
 

src/video_core/shader/decode/xmad.cpp

@@ -42,9 +42,9 @@ u32 ShaderIR::DecodeXmad(BasicBlock& bb, u32 pc) {
         case OpCode::Id::XMAD_IMM:
             return {instr.xmad.merge_37, Immediate(static_cast<u32>(instr.xmad.imm20_16)),
                     GetRegister(instr.gpr39)};
-        default:
-            UNIMPLEMENTED_MSG("Unhandled XMAD instruction: {}", opcode->get().GetName());
         }
+        UNIMPLEMENTED_MSG("Unhandled XMAD instruction: {}", opcode->get().GetName());
+        return {false, Immediate(0), Immediate(0)};
     }();
 
     if (instr.xmad.high_a) {
@@ -85,9 +85,9 @@ u32 ShaderIR::DecodeXmad(BasicBlock& bb, u32 pc) {
                                                    NO_PRECISE, original_b, Immediate(16));
             return SignedOperation(OperationCode::IAdd, is_signed_c, NO_PRECISE, op_c, shifted_b);
         }
-        default: {
+        default:
             UNIMPLEMENTED_MSG("Unhandled XMAD mode: {}", static_cast<u32>(instr.xmad.mode.Value()));
-        }
+            return Immediate(0);
         }
     }();