Import of the watch repository from Pebble

src/libos/README.md

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+# libOS
+
+libOS is a helper library that makes developing software on top of FreeRTOS on ARM easier.
+It is used by and built for the main FW and the Dialog Bluetooth FW.
+
+## Dependencies:
+
+- libc
+- libutil
+- FreeRTOS
+- Availability of an <mcu.h> header file that includes the CMSIS headers (core_cmX.h,
+  core_cmFunc.h, etc.)
+- A handful of platform specific functions, see platform.c

src/libos/include/mcu/cache.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+// Instruction cache and data cache are entirely separate. Therefore, you must both flush data
+// cache _and_ invalidate instruction cache for that region in order to properly execute new code.
+
+// A cache flush means the data is written out from the cache into memory. A cache invalidate
+// means the data in the cache is thrown out and will be reloaded from memory on the next access.
+// A flush does keep the data still in cache, so if you want to write out and invalidate, you want
+// to use flush_invalidate.
+
+// All cache operations MUST operate on the cache line size. You can safely flush memory that isn't
+// part of your buffer, but invalidation CAN AND WILL destroy other memory! Be very careful!
+
+// The cache line size on Cortex-M7 is 32 bytes.
+
+//! Enable instruction cache.
+void icache_enable(void);
+//! Disable instruction cache.
+void icache_disable(void);
+//! Returns whether or not ICache is enabled
+bool icache_is_enabled(void);
+//! Returns line size of ICache.
+uint32_t icache_line_size(void);
+
+//! Invalidate entire instruction cache.
+void icache_invalidate_all(void);
+//! Invalidate instruction cache for `addr` for `size` bytes.
+//! `addr` and `size` should both be aligned by the cache line size.
+void icache_invalidate(void *addr, size_t size);
+
+//! Enable data cache.
+void dcache_enable(void);
+//! Disable data cache.
+void dcache_disable(void);
+//! Returns whether or not DCache is enabled
+bool dcache_is_enabled(void);
+//! Returns line size of DCache.
+uint32_t dcache_line_size(void);
+
+//! Flush entire data cache.
+void dcache_flush_all(void);
+//! Invalidate entire data cache.
+void dcache_invalidate_all(void);
+//! Flush, then invalidate entire data cache.
+void dcache_flush_invalidate_all(void);
+
+//! Flush data cache for `addr` for `size` bytes.
+//! `addr` and `size` should both be aligned by the cache line size.
+void dcache_flush(const void *addr, size_t size);
+//! Invalidate data cache for `addr` for `size` bytes.
+//! `addr` and `size` should both be aligned by the cache line size.
+void dcache_invalidate(void *addr, size_t size);
+//! Flush, then invalidate data cache for `addr` for `size` bytes.
+//! `addr` and `size` should both be aligned by the cache line size.
+void dcache_flush_invalidate(const void *addr, size_t size);
+
+//! Aligns an address and size so that they are both aligned to the ICache line size, and still
+//! covers the range requested.
+void icache_align(uintptr_t *addr, size_t *size);
+//! Aligns an address and size so that they are both aligned to the DCache line size, and still
+//! covers the range requested.
+void dcache_align(uintptr_t *addr, size_t *size);
+
+//! For aligning things to work with the data cache, you will want to check what the cache line
+//! size is, and align accordingly. However, the hardware peripheral also might require a minimum
+//! alignment. So you pass the minimum alignment in bytes into `min`, and the return value is the
+//! mask you can apply to get the minimum aligned address.
+uint32_t dcache_alignment_mask_minimum(uint32_t min);

src/libos/include/mcu/fpu.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+void mcu_fpu_cleanup(void);

src/libos/include/mcu/interrupts.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+
+inline static bool mcu_state_is_isr(void);
+
+//! Return the priority level of the currently executing exception handler.
+//! Returns ~0 if not in an exception handler. Lower numbers mean higher
+//! priority. Anything below 0xB should not execute any FreeRTOS calls.
+inline static uint32_t mcu_state_get_isr_priority(void);
+
+bool mcu_state_are_interrupts_enabled(void);
+
+#ifdef __arm__
+#include "mcu/interrupts_arm.inl.h"
+#else
+#include "mcu/interrupts_stubs.inl.h"
+#endif

src/libos/include/mcu/interrupts_arm.inl.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define CMSIS_COMPATIBLE
+#include <mcu.h>
+
+static inline bool mcu_state_is_isr(void) {
+  return __get_IPSR() != 0;
+}
+
+static inline uint32_t mcu_state_get_isr_priority(void) {
+  uint32_t exc_number  = __get_IPSR();
+  if (exc_number == 0) {
+    return ~0;
+  }
+  // Exception numbers 0 -> 15 are "internal" interrupts and NVIC_GetPriority() expects them to be
+  // negative numbers.
+  return NVIC_GetPriority((int)exc_number - 16);
+}

src/libos/include/mcu/interrupts_stubs.inl.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static inline bool mcu_state_is_isr(void) {
+  return false;
+}
+
+static inline uint32_t mcu_state_get_isr_priority(void) {
+  return ~0;
+}

src/libos/include/mcu/privilege.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include <stdbool.h>
+
+inline static bool mcu_state_is_thread_privileged(void);
+
+//! Update the thread mode privilege bit in the control register. Note that you
+//! must already be privileged to call this with a true argument.
+void mcu_state_set_thread_privilege(bool privilege);
+
+bool mcu_state_is_privileged(void);
+
+#ifdef __arm__
+#include "mcu/privilege_arm.inl.h"
+#else
+#include "mcu/privilege_stubs.inl.h"
+#endif

src/libos/include/mcu/privilege_arm.inl.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define CMSIS_COMPATIBLE
+#include <mcu.h>
+
+
+//! @file privilege_arm.inl.h
+//! Helpful functions for dealing with our micros execution state.
+//!
+//! Functions in this file muck with the control register. This register is described here:
+//! http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf page 2-9
+//! We only really care about the 0th bit.
+//! [0] nPriv Defines the Thread mode privilege level
+//!           0 = Privileged
+//!           1 = Unprivileged
+//! This variable can be read in both modes, but only may be written in privileged mode.
+
+// See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/CHDIGFCA.html
+// for a more detailed explanation of these various privilege states.
+
+static inline bool mcu_state_is_thread_privileged(void) {
+  return (__get_CONTROL() & 0x1) == 0;
+}

src/libos/include/mcu/privilege_stubs.inl.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "util/attributes.h"
+
+static inline bool mcu_state_is_thread_privileged(void) {
+  return true;
+}
+
+void WEAK mcu_state_set_thread_privilege(bool privilege) {
+}
+
+bool WEAK mcu_state_is_privileged(void) {
+  return true;
+}

src/libos/include/os/assert.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include "util/attributes.h"
+#include "util/likely.h"
+
+#include <stdint.h>
+
+NORETURN os_assertion_failed(const char *filename, int line);
+NORETURN os_assertion_failed_lr(const char *filename, int line, uint32_t lr);
+
+#define OS_ASSERT(expr) \
+  do { \
+    if (UNLIKELY(!(expr))) { \
+      os_assertion_failed(__FILE_NAME__, __LINE__); \
+    } \
+  } while (0)
+
+#define OS_ASSERT_LR(expr, lr) \
+  do { \
+    if (UNLIKELY(!(expr))) { \
+      os_assertion_failed_lr(__FILE_NAME__, __LINE__, lr); \
+    } \
+  } while (0)

src/libos/include/os/malloc.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include <stddef.h>
+
+void *os_malloc(size_t size);
+void *os_malloc_check(size_t size);
+void os_free(void *ptr);

src/libos/include/os/mutex.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+
+
+#include "util/list.h"
+
+struct pebble_mutex_t;
+typedef struct pebble_mutex_t PebbleMutex;
+struct pebble_recursive_mutex_t;
+typedef struct pebble_recursive_mutex_t PebbleRecursiveMutex;
+
+#define INVALID_MUTEX_HANDLE 0
+
+//! @return INVALID_MUTEX_HANDLE if failed, success otherwise.
+PebbleMutex *mutex_create(void);
+
+void mutex_destroy(PebbleMutex *handle);
+
+void mutex_lock(PebbleMutex *handle);
+
+bool mutex_lock_with_timeout(PebbleMutex *handle, uint32_t timeout_ms);
+
+void mutex_lock_with_lr(PebbleMutex *handle, uint32_t myLR);
+
+void mutex_unlock(PebbleMutex *handle);
+
+PebbleRecursiveMutex * mutex_create_recursive(void);
+
+void mutex_lock_recursive(PebbleRecursiveMutex *handle);
+
+bool mutex_lock_recursive_with_timeout(PebbleRecursiveMutex *handle, uint32_t timeout_ms);
+
+bool mutex_lock_recursive_with_timeout_and_lr(PebbleRecursiveMutex *handle,
+                                              uint32_t timeout_ms,
+                                              uint32_t LR);
+
+//! Tests if a given mutex is owned by the current task. Useful for
+//! ensuring locks are held when they should be.
+bool mutex_is_owned_recursive(PebbleRecursiveMutex *handle);
+
+void mutex_unlock_recursive(PebbleRecursiveMutex *handle);
+
+//! @return true if the calling task owns the mutex
+void mutex_assert_held_by_curr_task(PebbleMutex *handle, bool is_held);
+
+//! @return true if the calling task owns the mutex
+void mutex_assert_recursive_held_by_curr_task(PebbleRecursiveMutex *handle, bool is_held);

src/libos/include/os/tick.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include "portmacro.h"
+
+#include <stdint.h>
+
+TickType_t milliseconds_to_ticks(uint32_t milliseconds);
+
+uint32_t ticks_to_milliseconds(TickType_t ticks);

src/libos/mcu/cache_arm.c

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mcu/cache.h"
+#include "util/attributes.h"
+
+#define CMSIS_COMPATIBLE
+#include <mcu.h>
+
+// I-Cache definition doesn't always exist
+#ifndef __ICACHE_PRESENT
+# define __ICACHE_PRESENT 0U
+#endif
+
+// D-Cache definition doesn't always exist
+#ifndef __DCACHE_PRESENT
+# define __DCACHE_PRESENT 0U
+#endif
+
+// Most of these implementations are derived from CMSIS
+#define CCSIDR_LINESIZE(x) (((x) & SCB_CCSIDR_LINESIZE_Msk) >> SCB_CCSIDR_LINESIZE_Pos)
+#define CCSIDR_WAYS(x)     (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+
+#define CSSELR_L1_DCACHE 0
+#define CSSELR_L1_ICACHE 1
+
+#if __ICACHE_PRESENT
+static uint32_t s_icache_cssidr;
+#endif
+
+#if __DCACHE_PRESENT
+static uint32_t s_dcache_cssidr;
+#endif
+
+#if __ICACHE_PRESENT || __DCACHE_PRESENT
+static uint32_t prv_get_line_size(uint32_t ccsidr) {
+  return ((CCSIDR_LINESIZE(ccsidr)) + 1) << 4;
+}
+
+static void prv_cache_operation_range(volatile uint32_t *reg, uint32_t line_size, uintptr_t addr,
+                                      size_t size) {
+  intptr_t op_size = size;
+
+  __DSB();
+  __ISB();
+
+  while (op_size > 0) {
+    *reg = addr;
+    addr += line_size;
+    op_size -= line_size;
+  }
+
+  __DSB();
+  __ISB();
+}
+#endif
+
+#if __DCACHE_PRESENT
+static void prv_dcache_operation_all(volatile uint32_t *reg) {
+  uint32_t ccsidr;
+  uint32_t sets;
+  uint32_t ways;
+
+  ccsidr = s_dcache_cssidr;
+
+  sets = CCSIDR_SETS(ccsidr);
+  do {
+    ways = CCSIDR_WAYS(ccsidr);
+    do {
+      *reg = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+              ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk));
+#if defined(__CC_ARM)
+      __schedule_barrier();
+#endif
+    } while (ways--);
+  } while (sets--);
+
+  __DSB();
+  __ISB();
+}
+#endif
+
+MOCKABLE void icache_enable(void) {
+#if __ICACHE_PRESENT
+  SCB->CSSELR = CSSELR_L1_ICACHE;
+  __DMB();
+  s_icache_cssidr = SCB->CCSIDR;
+
+  icache_invalidate_all();
+
+  __DSB();
+  __ISB();
+  SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache
+  __DSB();
+  __ISB();
+#endif
+}
+
+MOCKABLE void icache_disable(void) {
+#if __ICACHE_PRESENT
+  __DSB();
+  __ISB();
+  SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache
+  __DSB();
+  __ISB();
+
+  icache_invalidate_all();
+#endif
+}
+
+MOCKABLE bool icache_is_enabled(void) {
+#if __ICACHE_PRESENT
+  return SCB->CCR & SCB_CCR_IC_Msk;
+#endif
+  return false;
+}
+
+MOCKABLE uint32_t icache_line_size(void) {
+#if __ICACHE_PRESENT
+  return prv_get_line_size(s_icache_cssidr);
+#endif
+  return 1;
+}
+
+
+MOCKABLE void dcache_enable(void) {
+#if __DCACHE_PRESENT
+  SCB->CSSELR = CSSELR_L1_DCACHE;
+  __DMB();
+  s_dcache_cssidr = SCB->CCSIDR;
+
+  dcache_invalidate_all();
+  __DSB();
+  SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache
+  __DSB();
+  __ISB();
+#endif
+}
+
+MOCKABLE void dcache_disable(void) {
+#if __DCACHE_PRESENT
+  dcache_flush_invalidate_all();
+  __DSB();
+  SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache
+  __DSB();
+  __ISB();
+#endif
+}
+
+MOCKABLE bool dcache_is_enabled(void) {
+#if __DCACHE_PRESENT
+  return SCB->CCR & SCB_CCR_DC_Msk;
+#endif
+  return false;
+}
+
+MOCKABLE uint32_t dcache_line_size(void) {
+#if __DCACHE_PRESENT
+  return prv_get_line_size(s_dcache_cssidr);
+#endif
+  return 1;
+}
+
+MOCKABLE uint32_t dcache_alignment_mask_minimum(uint32_t min) {
+#if __DCACHE_PRESENT
+  const uint32_t line_size = dcache_line_size();
+  if (line_size > min) {
+    return line_size - 1;
+  }
+#endif
+  return min - 1;
+}
+
+MOCKABLE void icache_invalidate_all(void) {
+#if __ICACHE_PRESENT
+  __DSB();
+  __ISB();
+  SCB->ICIALLU = 0;
+  __DSB();
+  __ISB();
+#endif
+}
+
+MOCKABLE void icache_invalidate(void *addr, size_t size) {
+#if __ICACHE_PRESENT
+  prv_cache_operation_range(&SCB->ICIMVAU, icache_line_size(), (uintptr_t)addr, size);
+#endif
+}
+
+MOCKABLE void dcache_flush_all(void) {
+#if __DCACHE_PRESENT
+  prv_dcache_operation_all(&SCB->DCCSW);
+#endif
+}
+
+MOCKABLE void dcache_invalidate_all(void) {
+#if __DCACHE_PRESENT
+  prv_dcache_operation_all(&SCB->DCISW);
+#endif
+}
+
+MOCKABLE void dcache_flush_invalidate_all(void) {
+#if __DCACHE_PRESENT
+  prv_dcache_operation_all(&SCB->DCCISW);
+#endif
+}
+
+MOCKABLE void dcache_flush(const void *addr, size_t size) {
+#if __DCACHE_PRESENT
+  prv_cache_operation_range(&SCB->DCCMVAC, dcache_line_size(), (uintptr_t)addr, size);
+#endif
+}
+
+MOCKABLE void dcache_invalidate(void *addr, size_t size) {
+#if __DCACHE_PRESENT
+  prv_cache_operation_range(&SCB->DCIMVAC, dcache_line_size(), (uintptr_t)addr, size);
+#endif
+}
+
+MOCKABLE void dcache_flush_invalidate(const void *addr, size_t size) {
+#if __DCACHE_PRESENT
+  prv_cache_operation_range(&SCB->DCCIMVAC, dcache_line_size(), (uintptr_t)addr, size);
+#endif
+}
+
+static void prv_align(uintptr_t *addr, size_t *size, uint32_t line_size) {
+  uint32_t line_mask = line_size - 1;
+  if (*addr & line_mask) {
+    // Need to adjust the address and size because the address is unaligned.
+    *size += *addr & line_mask;
+    *addr &= ~line_mask;
+  }
+  if (*size & line_mask) {
+    // Need to round the size up because the size is unaligned.
+    *size = (*size + line_mask) & ~line_mask;
+  }
+}
+
+void icache_align(uintptr_t *addr, size_t *size) {
+  prv_align(addr, size, icache_line_size());
+}
+
+void dcache_align(uintptr_t *addr, size_t *size) {
+  prv_align(addr, size, dcache_line_size());
+}

src/libos/mcu/fpu_arm.c

@@ -0,0 +1,39 @@
+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mcu/fpu.h"
+
+#define CMSIS_COMPATIBLE
+#include <mcu.h>
+
+#include <stdint.h>
+
+void mcu_fpu_cleanup(void) {
+  // The lazy stacking mechanism for the Cortex M4 starts stacking FPU
+  // registers during context switches once the thread has used the FPU
+  // once. This is problematic because this bumps the stack cost of a context
+  // switch by an additional 132 bytes. This routine resets the FPCA bit which
+  // controls whether or not this stacking takes place
+  // For the Cortex M3, this routine is a no-op
+
+  const uint32_t fpca_bit_mask = 0x4;
+  uint32_t control = __get_CONTROL();
+
+  if ((control & fpca_bit_mask) != 0) {
+    control &= ~fpca_bit_mask;
+    __set_CONTROL(control);
+  }
+}

src/libos/mcu/interrupts_arm.c

@@ -0,0 +1,22 @@
+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mcu/interrupts.h"
+
+bool mcu_state_are_interrupts_enabled(void) {
+  // When this bit is set, all interrupts (of configureable priority) are disabled
+  return ((__get_PRIMASK() & 0x1) == 0x0);
+}

src/libos/mcu/privilege_arm.c

@@ -0,0 +1,35 @@
+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mcu/privilege.h"
+
+#include "mcu/interrupts.h"
+#include "util/attributes.h"
+
+// These functions need to be called from assembly so they can't be inlined
+EXTERNALLY_VISIBLE void mcu_state_set_thread_privilege(bool privileged) {
+  uint32_t control = __get_CONTROL();
+  if (privileged) {
+    control &= ~0x1;
+  } else {
+    control |= 0x1;
+  }
+  __set_CONTROL(control);
+}
+
+bool mcu_state_is_privileged(void) {
+  return mcu_state_is_thread_privileged() || mcu_state_is_isr();
+}

src/libos/mutex_freertos.c

@@ -0,0 +1,191 @@
+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mcu/interrupts.h"
+#include "os/assert.h"
+#include "os/malloc.h"
+#include "os/mutex.h"
+#include "os/tick.h"
+
+#include "FreeRTOS.h"
+#include "light_mutex.h"
+#include "task.h"
+
+#include <string.h>
+
+typedef struct {
+    uint32_t lr;
+    LightMutexHandle_t freertos_mutex;
+} PebbleMutexCommon;
+
+struct pebble_mutex_t {
+  PebbleMutexCommon common;
+};
+
+struct pebble_recursive_mutex_t {
+  PebbleMutexCommon common;
+};
+
+// macros should only be called while we hold the mutex we are logging so no
+// additional locking is needed
+#define LOG_LOCKED(logged_lr, new_lr)    \
+  if (logged_lr == 0) {              \
+    logged_lr = new_lr;              \
+  }
+
+#define LOG_UNLOCKED(logged_lr, nest_count) \
+  if (nest_count == 1) {                \
+    logged_lr = 0;                      \
+  }
+
+static PebbleMutexCommon *create_pebble_mutex(LightMutexHandle_t freertos_mutex) {
+  PebbleMutexCommon *mutex = os_malloc_check(sizeof(PebbleMutex));
+  *mutex = (PebbleMutexCommon) {
+    .freertos_mutex = freertos_mutex,
+    .lr = 0
+  };
+
+  return mutex;
+}
+
+PebbleMutex * mutex_create(void) {
+  LightMutexHandle_t freertos_mutex = xLightMutexCreate();
+  OS_ASSERT(freertos_mutex != NULL);
+  PebbleMutex *mutex = (PebbleMutex *)create_pebble_mutex(freertos_mutex);
+  return mutex;
+}
+
+void mutex_destroy(PebbleMutex * handle) {
+  OS_ASSERT(handle != NULL);
+  LightMutexHandle_t mutex = handle->common.freertos_mutex;
+  vLightMutexDelete(mutex);
+  os_free(handle);
+}
+
+void mutex_lock(PebbleMutex * handle) {
+  uintptr_t myLR = (uintptr_t) __builtin_return_address(0);
+
+  OS_ASSERT(!mcu_state_is_isr());
+
+  xLightMutexLock(handle->common.freertos_mutex, portMAX_DELAY);
+  LOG_LOCKED(handle->common.lr, myLR);
+}
+
+bool mutex_lock_with_timeout(PebbleMutex * handle, uint32_t timeout_ms) {
+  uintptr_t myLR = (uintptr_t) __builtin_return_address(0);
+
+  OS_ASSERT(!mcu_state_is_isr());
+
+  TickType_t timeout_ticks = milliseconds_to_ticks(timeout_ms);
+  LightMutexHandle_t mutex = handle->common.freertos_mutex;
+
+  if (xLightMutexLock(mutex, timeout_ticks) == pdTRUE) {
+    LOG_LOCKED(handle->common.lr, myLR);
+    return (true);
+  }
+
+  return (false);
+}
+
+void mutex_lock_with_lr(PebbleMutex * handle, uint32_t myLR) {
+  OS_ASSERT(!mcu_state_is_isr());
+
+  xLightMutexLock(handle->common.freertos_mutex, portMAX_DELAY);
+  LOG_LOCKED(handle->common.lr, myLR);
+}
+
+void mutex_unlock(PebbleMutex * handle) {
+  OS_ASSERT(!mcu_state_is_isr());
+  LOG_UNLOCKED(handle->common.lr, 1)
+  xLightMutexUnlock(handle->common.freertos_mutex);
+}
+
+static void prv_assert_held_by_curr_task(PebbleMutex * handle, bool is_held, uint32_t lr) {
+  LightMutexHandle_t mutex = handle->common.freertos_mutex;
+  OS_ASSERT_LR((xLightMutexGetHolder(mutex) == xTaskGetCurrentTaskHandle()) == is_held,
+                 lr);
+}
+
+void mutex_assert_held_by_curr_task(PebbleMutex * handle, bool is_held) {
+  uintptr_t saved_lr = (uintptr_t) __builtin_return_address(0);
+  prv_assert_held_by_curr_task(handle, is_held, saved_lr);
+}
+
+void mutex_assert_recursive_held_by_curr_task(PebbleRecursiveMutex * handle, bool is_held) {
+  uintptr_t saved_lr = (uintptr_t) __builtin_return_address(0);
+  prv_assert_held_by_curr_task((PebbleMutex *) handle, is_held, saved_lr);
+}
+
+PebbleRecursiveMutex * mutex_create_recursive(void) {
+  LightMutexHandle_t freertos_mutex = xLightMutexCreateRecursive();
+  OS_ASSERT(freertos_mutex != NULL);
+  PebbleRecursiveMutex * mutex = (PebbleRecursiveMutex *)create_pebble_mutex(freertos_mutex);
+
+  return mutex;
+}
+
+void mutex_lock_recursive(PebbleRecursiveMutex * handle) {
+  uintptr_t myLR = (uintptr_t) __builtin_return_address(0);
+  OS_ASSERT(!mcu_state_is_isr());
+  xLightMutexLockRecursive(handle->common.freertos_mutex, portMAX_DELAY);
+  LOG_LOCKED(handle->common.lr, myLR);
+}
+
+bool mutex_lock_recursive_with_timeout_and_lr(PebbleRecursiveMutex * handle,
+    uint32_t timeout_ms, uint32_t myLR) {
+  OS_ASSERT(!mcu_state_is_isr());
+
+  TickType_t timeout_ticks = milliseconds_to_ticks(timeout_ms);
+  LightMutexHandle_t mutex = handle->common.freertos_mutex;
+
+  if (xLightMutexLockRecursive(mutex, timeout_ticks) == pdTRUE) {
+    LOG_LOCKED(handle->common.lr, myLR);
+    return (true);
+  }
+
+  return (false);
+}
+
+bool mutex_lock_recursive_with_timeout(PebbleRecursiveMutex * handle, uint32_t timeout_ms) {
+  uintptr_t myLR = (uintptr_t) __builtin_return_address(0);
+
+  OS_ASSERT(!mcu_state_is_isr());
+
+  TickType_t timeout_ticks = milliseconds_to_ticks(timeout_ms);
+  LightMutexHandle_t mutex = handle->common.freertos_mutex;
+
+  if (xLightMutexLockRecursive(mutex, timeout_ticks) == pdTRUE) {
+    LOG_LOCKED(handle->common.lr, myLR);
+    return (true);
+  }
+
+  return (false);
+}
+
+bool mutex_is_owned_recursive(PebbleRecursiveMutex * handle) {
+  LightMutexHandle_t mutex = handle->common.freertos_mutex;
+  void* holder = xLightMutexGetHolder(mutex);
+  void* current = xTaskGetCurrentTaskHandle();
+  return (holder == current);
+}
+
+void mutex_unlock_recursive(PebbleRecursiveMutex * handle) {
+  OS_ASSERT(!mcu_state_is_isr());
+  LightMutexHandle_t mutex = handle->common.freertos_mutex;
+  LOG_UNLOCKED(handle->common.lr, uxLightMutexGetRecursiveCallCount(mutex));
+  xLightMutexUnlockRecursive(mutex);
+}
+

src/libos/platform.c

@@ -0,0 +1,55 @@
+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "os/malloc.h"
+#include "os/assert.h"
+#include "util/attributes.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+
+// Below are some default implementations for system-specific functions required by libos.
+// These functions assume a working C standard library is linked into the program.
+// For programs where this isn't the case (e.g. the Pebble FW),
+// alternate implementations need to be provided.
+// The functions are defined as WEAK so they may be easily overridden.
+
+WEAK void os_log(const char *filename, int line, const char *string) {
+  printf("%s:%d %s\n", filename, line, string);
+}
+
+WEAK NORETURN os_assertion_failed(const char *filename, int line) {
+  os_log(filename, line, "*** OS ASSERT FAILED");
+  exit(EXIT_FAILURE);
+}
+
+WEAK NORETURN os_assertion_failed_lr(const char *filename, int line, uint32_t lr) {
+  os_assertion_failed(filename, line);
+}
+
+WEAK void *os_malloc(size_t size) {
+  return malloc(size);
+}
+
+WEAK void *os_malloc_check(size_t size) {
+  void *ptr = malloc(size);
+  OS_ASSERT(ptr);
+  return ptr;
+}
+
+WEAK void os_free(void *ptr) {
+  free(ptr);
+}

src/libos/tick.c

@@ -0,0 +1,28 @@
+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "FreeRTOS.h"
+#include "portmacro.h"
+
+#include <stdint.h>
+
+TickType_t milliseconds_to_ticks(uint32_t milliseconds) {
+  return ((uint64_t)milliseconds * configTICK_RATE_HZ) / 1000;
+}
+
+TickType_t ticks_to_milliseconds(uint32_t ticks) {
+  return ((uint64_t)ticks * 1000) / configTICK_RATE_HZ;
+}

src/libos/wscript

@@ -0,0 +1,25 @@
+import waftools
+
+
+def build(bld):
+    sources = bld.path.ant_glob('**/*.c')
+
+    def build_lib(target, env, platform_uses):
+        # Build the directory using firmware environment
+        bld.stlib(source=sources,
+                  target=target,
+                  includes=['.', 'include'],
+                  use=['pblibc_includes',
+                       'libutil_includes'] + platform_uses,
+                  env=env.derive())
+
+    bld(export_includes=['include'], name='libos_includes')
+
+    if bld.env in (bld.all_envs['local'], bld.all_envs['32bit']):
+        # Skip building sources for local builds, like unit tests.
+        return
+
+    build_lib('libos', bld.env, ['fw_includes', 'freertos'])
+
+
+# vim:filetype=python