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video_core: Implement conversion for uncommon/unsupported number formats. (#2047)
* video_core: Implement conversion for uncommon/unsupported number formats. * shader_recompiler: Reinterpret image sample output as well. * liverpool_to_vk: Remove mappings for remapped number formats. These were poorly supported by drivers anyway. * resource_tracking_pass: Fix image write swizzle mistake. * amdgpu: Add missing specialization and move format mapping data to types * reinterpret: Fix U/SToF input type.
This commit is contained in:
squidbus
GitHub
parent
c3ecf599ad
commit
b0d7feb292
12 changed files with 486 additions and 385 deletions
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@ -2,6 +2,7 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/ir/reinterpret.h"
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#include "shader_recompiler/runtime_info.h"
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namespace Shader::Gcn {
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@ -31,14 +32,16 @@ void Translator::EmitExport(const GcnInst& inst) {
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return;
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}
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const u32 index = u32(attrib) - u32(IR::Attribute::RenderTarget0);
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const auto [r, g, b, a] = runtime_info.fs_info.color_buffers[index].swizzle;
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const auto col_buf = runtime_info.fs_info.color_buffers[index];
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const auto converted = IR::ApplyWriteNumberConversion(ir, value, col_buf.num_conversion);
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const auto [r, g, b, a] = col_buf.swizzle;
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const std::array swizzle_array = {r, g, b, a};
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const auto swizzled_comp = swizzle_array[comp];
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if (u32(swizzled_comp) < u32(AmdGpu::CompSwizzle::Red)) {
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ir.SetAttribute(attrib, value, comp);
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ir.SetAttribute(attrib, converted, comp);
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return;
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}
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ir.SetAttribute(attrib, value, u32(swizzled_comp) - u32(AmdGpu::CompSwizzle::Red));
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ir.SetAttribute(attrib, converted, u32(swizzled_comp) - u32(AmdGpu::CompSwizzle::Red));
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};
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const auto unpack = [&](u32 idx) {
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@ -301,8 +301,7 @@ s32 TryHandleInlineCbuf(IR::Inst& inst, Info& info, Descriptors& descriptors,
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});
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}
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void PatchBufferInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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Descriptors& descriptors) {
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void PatchBufferSharp(IR::Block& block, IR::Inst& inst, Info& info, Descriptors& descriptors) {
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s32 binding{};
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AmdGpu::Buffer buffer;
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if (binding = TryHandleInlineCbuf(inst, info, descriptors, buffer); binding == -1) {
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@ -317,19 +316,191 @@ void PatchBufferInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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});
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}
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// Update buffer descriptor format.
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const auto inst_info = inst.Flags<IR::BufferInstInfo>();
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// Replace handle with binding index in buffer resource list.
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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inst.SetArg(0, ir.Imm32(binding));
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}
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void PatchTextureBufferSharp(IR::Block& block, IR::Inst& inst, Info& info,
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Descriptors& descriptors) {
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const IR::Inst* handle = inst.Arg(0).InstRecursive();
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const IR::Inst* producer = handle->Arg(0).InstRecursive();
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const auto sharp = TrackSharp(producer, info);
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const s32 binding = descriptors.Add(TextureBufferResource{
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.sharp_idx = sharp,
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.is_written = inst.GetOpcode() == IR::Opcode::StoreBufferFormatF32,
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});
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// Replace handle with binding index in texture buffer resource list.
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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inst.SetArg(0, ir.Imm32(binding));
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}
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void PatchImageSharp(IR::Block& block, IR::Inst& inst, Info& info, Descriptors& descriptors) {
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const auto pred = [](const IR::Inst* inst) -> std::optional<const IR::Inst*> {
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const auto opcode = inst->GetOpcode();
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if (opcode == IR::Opcode::CompositeConstructU32x2 || // IMAGE_SAMPLE (image+sampler)
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opcode == IR::Opcode::ReadConst || // IMAGE_LOAD (image only)
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opcode == IR::Opcode::GetUserData) {
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return inst;
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}
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return std::nullopt;
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};
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const auto result = IR::BreadthFirstSearch(&inst, pred);
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ASSERT_MSG(result, "Unable to find image sharp source");
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const IR::Inst* producer = result.value();
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const bool has_sampler = producer->GetOpcode() == IR::Opcode::CompositeConstructU32x2;
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const auto tsharp_handle = has_sampler ? producer->Arg(0).InstRecursive() : producer;
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// Read image sharp.
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const auto tsharp = TrackSharp(tsharp_handle, info);
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const auto inst_info = inst.Flags<IR::TextureInstInfo>();
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auto image = info.ReadUdSharp<AmdGpu::Image>(tsharp);
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if (!image.Valid()) {
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LOG_ERROR(Render_Vulkan, "Shader compiled with unbound image!");
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image = AmdGpu::Image::Null();
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}
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ASSERT(image.GetType() != AmdGpu::ImageType::Invalid);
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const bool is_read = inst.GetOpcode() == IR::Opcode::ImageRead;
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const bool is_written = inst.GetOpcode() == IR::Opcode::ImageWrite;
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// Patch image instruction if image is FMask.
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if (image.IsFmask()) {
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ASSERT_MSG(!is_written, "FMask storage instructions are not supported");
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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switch (inst.GetOpcode()) {
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case IR::Opcode::ImageRead:
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case IR::Opcode::ImageSampleRaw: {
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IR::F32 fmaskx = ir.BitCast<IR::F32>(ir.Imm32(0x76543210));
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IR::F32 fmasky = ir.BitCast<IR::F32>(ir.Imm32(0xfedcba98));
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inst.ReplaceUsesWith(ir.CompositeConstruct(fmaskx, fmasky));
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return;
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}
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case IR::Opcode::ImageQueryLod:
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inst.ReplaceUsesWith(ir.Imm32(1));
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return;
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case IR::Opcode::ImageQueryDimensions: {
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IR::Value dims = ir.CompositeConstruct(ir.Imm32(static_cast<u32>(image.width)), // x
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ir.Imm32(static_cast<u32>(image.width)), // y
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ir.Imm32(1), ir.Imm32(1)); // depth, mip
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inst.ReplaceUsesWith(dims);
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// Track FMask resource to do specialization.
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descriptors.Add(FMaskResource{
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.sharp_idx = tsharp,
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});
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return;
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}
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default:
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UNREACHABLE_MSG("Can't patch fmask instruction {}", inst.GetOpcode());
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}
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}
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u32 image_binding = descriptors.Add(ImageResource{
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.sharp_idx = tsharp,
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.is_depth = bool(inst_info.is_depth),
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.is_atomic = IsImageAtomicInstruction(inst),
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.is_array = bool(inst_info.is_array),
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.is_read = is_read,
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.is_written = is_written,
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});
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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if (inst.GetOpcode() == IR::Opcode::ImageSampleRaw) {
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// Read sampler sharp.
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const auto [sampler_binding, sampler] = [&] -> std::pair<u32, AmdGpu::Sampler> {
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ASSERT(producer->GetOpcode() == IR::Opcode::CompositeConstructU32x2);
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const IR::Value& handle = producer->Arg(1);
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// Inline sampler resource.
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if (handle.IsImmediate()) {
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LOG_WARNING(Render_Vulkan, "Inline sampler detected");
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const auto inline_sampler = AmdGpu::Sampler{.raw0 = handle.U32()};
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const auto binding = descriptors.Add(SamplerResource{
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.sharp_idx = std::numeric_limits<u32>::max(),
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.inline_sampler = inline_sampler,
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});
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return {binding, inline_sampler};
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}
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// Normal sampler resource.
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const auto ssharp_handle = handle.InstRecursive();
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const auto& [ssharp_ud, disable_aniso] = TryDisableAnisoLod0(ssharp_handle);
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const auto ssharp = TrackSharp(ssharp_ud, info);
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const auto binding = descriptors.Add(SamplerResource{
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.sharp_idx = ssharp,
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.associated_image = image_binding,
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.disable_aniso = disable_aniso,
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});
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return {binding, info.ReadUdSharp<AmdGpu::Sampler>(ssharp)};
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}();
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// Patch image and sampler handle.
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inst.SetArg(0, ir.Imm32(image_binding | sampler_binding << 16));
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} else {
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// Patch image handle.
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inst.SetArg(0, ir.Imm32(image_binding));
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}
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}
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void PatchDataRingAccess(IR::Block& block, IR::Inst& inst, Info& info, Descriptors& descriptors) {
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// Insert gds binding in the shader if it doesn't exist already.
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// The buffer is used for append/consume counters.
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constexpr static AmdGpu::Buffer GdsSharp{.base_address = 1};
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const u32 binding = descriptors.Add(BufferResource{
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.used_types = IR::Type::U32,
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.inline_cbuf = GdsSharp,
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.is_gds_buffer = true,
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.is_written = true,
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});
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const auto pred = [](const IR::Inst* inst) -> std::optional<const IR::Inst*> {
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if (inst->GetOpcode() == IR::Opcode::GetUserData) {
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return inst;
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}
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return std::nullopt;
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};
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// Attempt to deduce the GDS address of counter at compile time.
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const u32 gds_addr = [&] {
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const IR::Value& gds_offset = inst.Arg(0);
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if (gds_offset.IsImmediate()) {
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// Nothing to do, offset is known.
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return gds_offset.U32() & 0xFFFF;
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}
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const auto result = IR::BreadthFirstSearch(&inst, pred);
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ASSERT_MSG(result, "Unable to track M0 source");
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// M0 must be set by some user data register.
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const IR::Inst* prod = gds_offset.InstRecursive();
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const u32 ud_reg = u32(result.value()->Arg(0).ScalarReg());
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u32 m0_val = info.user_data[ud_reg] >> 16;
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if (prod->GetOpcode() == IR::Opcode::IAdd32) {
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m0_val += prod->Arg(1).U32();
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}
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return m0_val & 0xFFFF;
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}();
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// Patch instruction.
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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inst.SetArg(0, ir.Imm32(gds_addr >> 2));
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inst.SetArg(1, ir.Imm32(binding));
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}
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void PatchBufferArgs(IR::Block& block, IR::Inst& inst, Info& info) {
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const auto handle = inst.Arg(0);
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const auto buffer_res = info.buffers[handle.U32()];
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const auto buffer = buffer_res.GetSharp(info);
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ASSERT(!buffer.add_tid_enable);
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// Address of constant buffer reads can be calculated at IR emittion time.
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// Address of constant buffer reads can be calculated at IR emission time.
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if (inst.GetOpcode() == IR::Opcode::ReadConstBuffer) {
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return;
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}
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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const auto inst_info = inst.Flags<IR::BufferInstInfo>();
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const IR::U32 index_stride = ir.Imm32(buffer.index_stride);
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const IR::U32 element_size = ir.Imm32(buffer.element_size);
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@ -366,21 +537,27 @@ void PatchBufferInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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inst.SetArg(1, address);
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}
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void PatchTextureBufferInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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Descriptors& descriptors) {
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const IR::Inst* handle = inst.Arg(0).InstRecursive();
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const IR::Inst* producer = handle->Arg(0).InstRecursive();
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const auto sharp = TrackSharp(producer, info);
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const auto buffer = info.ReadUdSharp<AmdGpu::Buffer>(sharp);
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const s32 binding = descriptors.Add(TextureBufferResource{
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.sharp_idx = sharp,
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.is_written = inst.GetOpcode() == IR::Opcode::StoreBufferFormatF32,
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});
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void PatchTextureBufferArgs(IR::Block& block, IR::Inst& inst, Info& info) {
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const auto handle = inst.Arg(0);
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const auto buffer_res = info.texture_buffers[handle.U32()];
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const auto buffer = buffer_res.GetSharp(info);
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// Replace handle with binding index in texture buffer resource list.
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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inst.SetArg(0, ir.Imm32(binding));
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ASSERT(!buffer.swizzle_enable && !buffer.add_tid_enable);
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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if (inst.GetOpcode() == IR::Opcode::StoreBufferFormatF32) {
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const auto swizzled = ApplySwizzle(ir, inst.Arg(2), buffer.DstSelect());
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const auto converted =
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ApplyWriteNumberConversionVec4(ir, swizzled, buffer.GetNumberConversion());
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inst.SetArg(2, converted);
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} else if (inst.GetOpcode() == IR::Opcode::LoadBufferFormatF32) {
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const auto inst_info = inst.Flags<IR::BufferInstInfo>();
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const auto texel = ir.LoadBufferFormat(inst.Arg(0), inst.Arg(1), inst_info);
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const auto swizzled = ApplySwizzle(ir, texel, buffer.DstSelect());
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const auto converted =
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ApplyReadNumberConversionVec4(ir, swizzled, buffer.GetNumberConversion());
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inst.ReplaceUsesWith(converted);
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}
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}
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IR::Value PatchCubeCoord(IR::IREmitter& ir, const IR::Value& s, const IR::Value& t,
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@ -409,39 +586,14 @@ IR::Value PatchCubeCoord(IR::IREmitter& ir, const IR::Value& s, const IR::Value&
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}
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}
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void PatchImageSampleInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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Descriptors& descriptors, const IR::Inst* producer,
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const u32 image_binding, const AmdGpu::Image& image) {
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// Read sampler sharp. This doesn't exist for IMAGE_LOAD/IMAGE_STORE instructions
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const auto [sampler_binding, sampler] = [&] -> std::pair<u32, AmdGpu::Sampler> {
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ASSERT(producer->GetOpcode() == IR::Opcode::CompositeConstructU32x2);
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const IR::Value& handle = producer->Arg(1);
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// Inline sampler resource.
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if (handle.IsImmediate()) {
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LOG_WARNING(Render_Vulkan, "Inline sampler detected");
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const auto inline_sampler = AmdGpu::Sampler{.raw0 = handle.U32()};
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const auto binding = descriptors.Add(SamplerResource{
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.sharp_idx = std::numeric_limits<u32>::max(),
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.inline_sampler = inline_sampler,
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});
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return {binding, inline_sampler};
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}
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// Normal sampler resource.
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const auto ssharp_handle = handle.InstRecursive();
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const auto& [ssharp_ud, disable_aniso] = TryDisableAnisoLod0(ssharp_handle);
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const auto ssharp = TrackSharp(ssharp_ud, info);
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const auto binding = descriptors.Add(SamplerResource{
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.sharp_idx = ssharp,
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.associated_image = image_binding,
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.disable_aniso = disable_aniso,
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});
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return {binding, info.ReadUdSharp<AmdGpu::Sampler>(ssharp)};
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}();
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void PatchImageSampleArgs(IR::Block& block, IR::Inst& inst, Info& info,
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const AmdGpu::Image& image) {
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const auto handle = inst.Arg(0);
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const auto sampler_res = info.samplers[(handle.U32() >> 16) & 0xFFFF];
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auto sampler = sampler_res.GetSharp(info);
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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const auto inst_info = inst.Flags<IR::TextureInstInfo>();
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const IR::U32 handle = ir.Imm32(image_binding | sampler_binding << 16);
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IR::Inst* body1 = inst.Arg(1).InstRecursive();
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IR::Inst* body2 = inst.Arg(2).InstRecursive();
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@ -539,8 +691,7 @@ void PatchImageSampleInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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// Query dimensions of image if needed for normalization.
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// We can't use the image sharp because it could be bound to a different image later.
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const auto dimensions =
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unnormalized ? ir.ImageQueryDimension(ir.Imm32(image_binding), ir.Imm32(0u), ir.Imm1(false))
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: IR::Value{};
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unnormalized ? ir.ImageQueryDimension(handle, ir.Imm32(0u), ir.Imm1(false)) : IR::Value{};
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const auto get_coord = [&](u32 coord_idx, u32 dim_idx) -> IR::Value {
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const auto coord = get_addr_reg(coord_idx);
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if (unnormalized) {
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@ -589,7 +740,7 @@ void PatchImageSampleInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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: IR::F32{};
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const IR::F32 lod_clamp = inst_info.has_lod_clamp ? get_addr_reg(addr_reg++) : IR::F32{};
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auto new_inst = [&] -> IR::Value {
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auto texel = [&] -> IR::Value {
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if (inst_info.is_gather) {
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if (inst_info.is_depth) {
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return ir.ImageGatherDref(handle, coords, offset, dref, inst_info);
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@ -611,94 +762,30 @@ void PatchImageSampleInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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}
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return ir.ImageSampleImplicitLod(handle, coords, bias, offset, inst_info);
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}();
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inst.ReplaceUsesWithAndRemove(new_inst);
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const auto converted = ApplyReadNumberConversionVec4(ir, texel, image.GetNumberConversion());
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inst.ReplaceUsesWith(converted);
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}
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void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descriptors& descriptors) {
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const auto pred = [](const IR::Inst* inst) -> std::optional<const IR::Inst*> {
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const auto opcode = inst->GetOpcode();
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if (opcode == IR::Opcode::CompositeConstructU32x2 || // IMAGE_SAMPLE (image+sampler)
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opcode == IR::Opcode::ReadConst || // IMAGE_LOAD (image only)
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opcode == IR::Opcode::GetUserData) {
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return inst;
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}
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return std::nullopt;
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};
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const auto result = IR::BreadthFirstSearch(&inst, pred);
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ASSERT_MSG(result, "Unable to find image sharp source");
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const IR::Inst* producer = result.value();
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const bool has_sampler = producer->GetOpcode() == IR::Opcode::CompositeConstructU32x2;
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const auto tsharp_handle = has_sampler ? producer->Arg(0).InstRecursive() : producer;
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// Read image sharp.
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const auto tsharp = TrackSharp(tsharp_handle, info);
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const auto inst_info = inst.Flags<IR::TextureInstInfo>();
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auto image = info.ReadUdSharp<AmdGpu::Image>(tsharp);
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if (!image.Valid()) {
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LOG_ERROR(Render_Vulkan, "Shader compiled with unbound image!");
|
||||
image = AmdGpu::Image::Null();
|
||||
}
|
||||
ASSERT(image.GetType() != AmdGpu::ImageType::Invalid);
|
||||
const bool is_read = inst.GetOpcode() == IR::Opcode::ImageRead;
|
||||
const bool is_written = inst.GetOpcode() == IR::Opcode::ImageWrite;
|
||||
|
||||
// Patch image instruction if image is FMask.
|
||||
if (image.IsFmask()) {
|
||||
ASSERT_MSG(!is_written, "FMask storage instructions are not supported");
|
||||
|
||||
IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
|
||||
switch (inst.GetOpcode()) {
|
||||
case IR::Opcode::ImageRead:
|
||||
case IR::Opcode::ImageSampleRaw: {
|
||||
IR::F32 fmaskx = ir.BitCast<IR::F32>(ir.Imm32(0x76543210));
|
||||
IR::F32 fmasky = ir.BitCast<IR::F32>(ir.Imm32(0xfedcba98));
|
||||
inst.ReplaceUsesWith(ir.CompositeConstruct(fmaskx, fmasky));
|
||||
return;
|
||||
}
|
||||
case IR::Opcode::ImageQueryLod:
|
||||
inst.ReplaceUsesWith(ir.Imm32(1));
|
||||
return;
|
||||
case IR::Opcode::ImageQueryDimensions: {
|
||||
IR::Value dims = ir.CompositeConstruct(ir.Imm32(static_cast<u32>(image.width)), // x
|
||||
ir.Imm32(static_cast<u32>(image.width)), // y
|
||||
ir.Imm32(1), ir.Imm32(1)); // depth, mip
|
||||
inst.ReplaceUsesWith(dims);
|
||||
|
||||
// Track FMask resource to do specialization.
|
||||
descriptors.Add(FMaskResource{
|
||||
.sharp_idx = tsharp,
|
||||
});
|
||||
return;
|
||||
}
|
||||
default:
|
||||
UNREACHABLE_MSG("Can't patch fmask instruction {}", inst.GetOpcode());
|
||||
}
|
||||
}
|
||||
|
||||
u32 image_binding = descriptors.Add(ImageResource{
|
||||
.sharp_idx = tsharp,
|
||||
.is_depth = bool(inst_info.is_depth),
|
||||
.is_atomic = IsImageAtomicInstruction(inst),
|
||||
.is_array = bool(inst_info.is_array),
|
||||
.is_read = is_read,
|
||||
.is_written = is_written,
|
||||
});
|
||||
|
||||
// Sample instructions must be resolved into a new instruction using address register data.
|
||||
if (inst.GetOpcode() == IR::Opcode::ImageSampleRaw) {
|
||||
PatchImageSampleInstruction(block, inst, info, descriptors, producer, image_binding, image);
|
||||
return;
|
||||
}
|
||||
|
||||
// Patch image handle
|
||||
IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
|
||||
inst.SetArg(0, ir.Imm32(image_binding));
|
||||
|
||||
// No need to patch coordinates if we are just querying.
|
||||
void PatchImageArgs(IR::Block& block, IR::Inst& inst, Info& info) {
|
||||
// Nothing to patch for dimension query.
|
||||
if (inst.GetOpcode() == IR::Opcode::ImageQueryDimensions) {
|
||||
return;
|
||||
}
|
||||
|
||||
const auto handle = inst.Arg(0);
|
||||
const auto image_res = info.images[handle.U32() & 0xFFFF];
|
||||
auto image = image_res.GetSharp(info);
|
||||
|
||||
// Sample instructions must be handled separately using address register data.
|
||||
if (inst.GetOpcode() == IR::Opcode::ImageSampleRaw) {
|
||||
PatchImageSampleArgs(block, inst, info, image);
|
||||
return;
|
||||
}
|
||||
|
||||
IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
|
||||
const auto inst_info = inst.Flags<IR::TextureInstInfo>();
|
||||
|
||||
// Now that we know the image type, adjust texture coordinate vector.
|
||||
IR::Inst* body = inst.Arg(1).InstRecursive();
|
||||
const auto [coords, arg] = [&] -> std::pair<IR::Value, IR::Value> {
|
||||
|
|
@ -719,152 +806,77 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
|
|||
case AmdGpu::ImageType::Color3D: // x, y, z, [lod]
|
||||
return {ir.CompositeConstruct(body->Arg(0), body->Arg(1), body->Arg(2)), body->Arg(3)};
|
||||
case AmdGpu::ImageType::Cube: // x, y, face, [lod]
|
||||
return {PatchCubeCoord(ir, body->Arg(0), body->Arg(1), body->Arg(2), is_written,
|
||||
inst_info.is_array),
|
||||
return {PatchCubeCoord(ir, body->Arg(0), body->Arg(1), body->Arg(2),
|
||||
inst.GetOpcode() == IR::Opcode::ImageWrite, inst_info.is_array),
|
||||
body->Arg(3)};
|
||||
default:
|
||||
UNREACHABLE_MSG("Unknown image type {}", image.GetType());
|
||||
}
|
||||
}();
|
||||
inst.SetArg(1, coords);
|
||||
|
||||
if (inst_info.has_lod) {
|
||||
ASSERT(inst.GetOpcode() == IR::Opcode::ImageRead ||
|
||||
inst.GetOpcode() == IR::Opcode::ImageWrite);
|
||||
ASSERT(image.GetType() != AmdGpu::ImageType::Color2DMsaa &&
|
||||
image.GetType() != AmdGpu::ImageType::Color2DMsaaArray);
|
||||
inst.SetArg(2, arg);
|
||||
} else if ((image.GetType() == AmdGpu::ImageType::Color2DMsaa ||
|
||||
image.GetType() == AmdGpu::ImageType::Color2DMsaaArray) &&
|
||||
(inst.GetOpcode() == IR::Opcode::ImageRead ||
|
||||
inst.GetOpcode() == IR::Opcode::ImageWrite)) {
|
||||
inst.SetArg(3, arg);
|
||||
}
|
||||
}
|
||||
const auto has_ms = image.GetType() == AmdGpu::ImageType::Color2DMsaa ||
|
||||
image.GetType() == AmdGpu::ImageType::Color2DMsaaArray;
|
||||
ASSERT(!inst_info.has_lod || !has_ms);
|
||||
const auto lod = inst_info.has_lod ? IR::U32{arg} : IR::U32{};
|
||||
const auto ms = has_ms ? IR::U32{arg} : IR::U32{};
|
||||
|
||||
void PatchTextureBufferInterpretation(IR::Block& block, IR::Inst& inst, Info& info) {
|
||||
const auto binding = inst.Arg(0).U32();
|
||||
const auto buffer_res = info.texture_buffers[binding];
|
||||
const auto buffer = buffer_res.GetSharp(info);
|
||||
if (!buffer.Valid()) {
|
||||
// Don't need to swizzle invalid buffer.
|
||||
return;
|
||||
}
|
||||
|
||||
IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
|
||||
if (inst.GetOpcode() == IR::Opcode::StoreBufferFormatF32) {
|
||||
inst.SetArg(2, ApplySwizzle(ir, inst.Arg(2), buffer.DstSelect()));
|
||||
} else if (inst.GetOpcode() == IR::Opcode::LoadBufferFormatF32) {
|
||||
const auto inst_info = inst.Flags<IR::BufferInstInfo>();
|
||||
const auto texel = ir.LoadBufferFormat(inst.Arg(0), inst.Arg(1), inst_info);
|
||||
const auto swizzled = ApplySwizzle(ir, texel, buffer.DstSelect());
|
||||
inst.ReplaceUsesWith(swizzled);
|
||||
}
|
||||
}
|
||||
|
||||
void PatchImageInterpretation(IR::Block& block, IR::Inst& inst, Info& info) {
|
||||
const auto binding = inst.Arg(0).U32();
|
||||
const auto image_res = info.images[binding & 0xFFFF];
|
||||
const auto image = image_res.GetSharp(info);
|
||||
if (!image.Valid() || !image_res.IsStorage(image)) {
|
||||
// Don't need to swizzle invalid or non-storage image.
|
||||
return;
|
||||
}
|
||||
|
||||
IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
|
||||
if (inst.GetOpcode() == IR::Opcode::ImageWrite) {
|
||||
inst.SetArg(4, ApplySwizzle(ir, inst.Arg(4), image.DstSelect()));
|
||||
} else if (inst.GetOpcode() == IR::Opcode::ImageRead) {
|
||||
const auto inst_info = inst.Flags<IR::TextureInstInfo>();
|
||||
const auto lod = inst.Arg(2);
|
||||
const auto ms = inst.Arg(3);
|
||||
const auto texel =
|
||||
ir.ImageRead(inst.Arg(0), inst.Arg(1), lod.IsEmpty() ? IR::U32{} : IR::U32{lod},
|
||||
ms.IsEmpty() ? IR::U32{} : IR::U32{ms}, inst_info);
|
||||
const auto swizzled = ApplySwizzle(ir, texel, image.DstSelect());
|
||||
inst.ReplaceUsesWith(swizzled);
|
||||
}
|
||||
}
|
||||
|
||||
void PatchDataRingInstruction(IR::Block& block, IR::Inst& inst, Info& info,
|
||||
Descriptors& descriptors) {
|
||||
// Insert gds binding in the shader if it doesn't exist already.
|
||||
// The buffer is used for append/consume counters.
|
||||
constexpr static AmdGpu::Buffer GdsSharp{.base_address = 1};
|
||||
const u32 binding = descriptors.Add(BufferResource{
|
||||
.used_types = IR::Type::U32,
|
||||
.inline_cbuf = GdsSharp,
|
||||
.is_gds_buffer = true,
|
||||
.is_written = true,
|
||||
});
|
||||
|
||||
const auto pred = [](const IR::Inst* inst) -> std::optional<const IR::Inst*> {
|
||||
if (inst->GetOpcode() == IR::Opcode::GetUserData) {
|
||||
return inst;
|
||||
const auto is_storage = image_res.IsStorage(image);
|
||||
if (inst.GetOpcode() == IR::Opcode::ImageRead) {
|
||||
auto texel = ir.ImageRead(handle, coords, lod, ms, inst_info);
|
||||
if (is_storage) {
|
||||
// Storage image requires shader swizzle.
|
||||
texel = ApplySwizzle(ir, texel, image.DstSelect());
|
||||
}
|
||||
return std::nullopt;
|
||||
};
|
||||
const auto converted =
|
||||
ApplyReadNumberConversionVec4(ir, texel, image.GetNumberConversion());
|
||||
inst.ReplaceUsesWith(converted);
|
||||
} else {
|
||||
inst.SetArg(1, coords);
|
||||
if (inst.GetOpcode() == IR::Opcode::ImageWrite) {
|
||||
inst.SetArg(2, lod);
|
||||
inst.SetArg(3, ms);
|
||||
|
||||
// Attempt to deduce the GDS address of counter at compile time.
|
||||
const u32 gds_addr = [&] {
|
||||
const IR::Value& gds_offset = inst.Arg(0);
|
||||
if (gds_offset.IsImmediate()) {
|
||||
// Nothing to do, offset is known.
|
||||
return gds_offset.U32() & 0xFFFF;
|
||||
auto texel = inst.Arg(4);
|
||||
if (is_storage) {
|
||||
// Storage image requires shader swizzle.
|
||||
texel = ApplySwizzle(ir, texel, image.DstSelect());
|
||||
}
|
||||
const auto converted =
|
||||
ApplyWriteNumberConversionVec4(ir, texel, image.GetNumberConversion());
|
||||
inst.SetArg(4, converted);
|
||||
}
|
||||
const auto result = IR::BreadthFirstSearch(&inst, pred);
|
||||
ASSERT_MSG(result, "Unable to track M0 source");
|
||||
|
||||
// M0 must be set by some user data register.
|
||||
const IR::Inst* prod = gds_offset.InstRecursive();
|
||||
const u32 ud_reg = u32(result.value()->Arg(0).ScalarReg());
|
||||
u32 m0_val = info.user_data[ud_reg] >> 16;
|
||||
if (prod->GetOpcode() == IR::Opcode::IAdd32) {
|
||||
m0_val += prod->Arg(1).U32();
|
||||
}
|
||||
return m0_val & 0xFFFF;
|
||||
}();
|
||||
|
||||
// Patch instruction.
|
||||
IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
|
||||
inst.SetArg(0, ir.Imm32(gds_addr >> 2));
|
||||
inst.SetArg(1, ir.Imm32(binding));
|
||||
}
|
||||
}
|
||||
|
||||
void ResourceTrackingPass(IR::Program& program) {
|
||||
// Iterate resource instructions and patch them after finding the sharp.
|
||||
auto& info = program.info;
|
||||
|
||||
// Pass 1: Track resource sharps
|
||||
Descriptors descriptors{info};
|
||||
for (IR::Block* const block : program.blocks) {
|
||||
for (IR::Inst& inst : block->Instructions()) {
|
||||
if (IsBufferInstruction(inst)) {
|
||||
PatchBufferInstruction(*block, inst, info, descriptors);
|
||||
continue;
|
||||
}
|
||||
if (IsTextureBufferInstruction(inst)) {
|
||||
PatchTextureBufferInstruction(*block, inst, info, descriptors);
|
||||
continue;
|
||||
}
|
||||
if (IsImageInstruction(inst)) {
|
||||
PatchImageInstruction(*block, inst, info, descriptors);
|
||||
continue;
|
||||
}
|
||||
if (IsDataRingInstruction(inst)) {
|
||||
PatchDataRingInstruction(*block, inst, info, descriptors);
|
||||
PatchBufferSharp(*block, inst, info, descriptors);
|
||||
} else if (IsTextureBufferInstruction(inst)) {
|
||||
PatchTextureBufferSharp(*block, inst, info, descriptors);
|
||||
} else if (IsImageInstruction(inst)) {
|
||||
PatchImageSharp(*block, inst, info, descriptors);
|
||||
} else if (IsDataRingInstruction(inst)) {
|
||||
PatchDataRingAccess(*block, inst, info, descriptors);
|
||||
}
|
||||
}
|
||||
}
|
||||
// Second pass to reinterpret format read/write where needed, since we now know
|
||||
// the bindings and their properties.
|
||||
|
||||
// Pass 2: Patch instruction args
|
||||
for (IR::Block* const block : program.blocks) {
|
||||
for (IR::Inst& inst : block->Instructions()) {
|
||||
if (IsTextureBufferInstruction(inst)) {
|
||||
PatchTextureBufferInterpretation(*block, inst, info);
|
||||
continue;
|
||||
}
|
||||
if (IsImageInstruction(inst)) {
|
||||
PatchImageInterpretation(*block, inst, info);
|
||||
if (IsBufferInstruction(inst)) {
|
||||
PatchBufferArgs(*block, inst, info);
|
||||
} else if (IsTextureBufferInstruction(inst)) {
|
||||
PatchTextureBufferArgs(*block, inst, info);
|
||||
} else if (IsImageInstruction(inst)) {
|
||||
PatchImageArgs(*block, inst, info);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
#pragma once
|
||||
|
||||
#include "shader_recompiler/ir/ir_emitter.h"
|
||||
#include "video_core/amdgpu/resource.h"
|
||||
#include "video_core/amdgpu/types.h"
|
||||
|
||||
namespace Shader::IR {
|
||||
|
||||
|
|
@ -21,4 +21,66 @@ inline Value ApplySwizzle(IREmitter& ir, const Value& vector, const AmdGpu::Comp
|
|||
return swizzled;
|
||||
}
|
||||
|
||||
/// Applies a number conversion in the read direction.
|
||||
inline F32 ApplyReadNumberConversion(IREmitter& ir, const F32& value,
|
||||
const AmdGpu::NumberConversion& conversion) {
|
||||
switch (conversion) {
|
||||
case AmdGpu::NumberConversion::None:
|
||||
return value;
|
||||
case AmdGpu::NumberConversion::UintToUscaled:
|
||||
return ir.ConvertUToF(32, 32, ir.BitCast<U32>(value));
|
||||
case AmdGpu::NumberConversion::SintToSscaled:
|
||||
return ir.ConvertSToF(32, 32, ir.BitCast<U32>(value));
|
||||
case AmdGpu::NumberConversion::UnormToUbnorm:
|
||||
// Convert 0...1 to -1...1
|
||||
return ir.FPSub(ir.FPMul(value, ir.Imm32(2.f)), ir.Imm32(1.f));
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
||||
inline Value ApplyReadNumberConversionVec4(IREmitter& ir, const Value& value,
|
||||
const AmdGpu::NumberConversion& conversion) {
|
||||
if (conversion == AmdGpu::NumberConversion::None) {
|
||||
return value;
|
||||
}
|
||||
const auto x = ApplyReadNumberConversion(ir, F32{ir.CompositeExtract(value, 0)}, conversion);
|
||||
const auto y = ApplyReadNumberConversion(ir, F32{ir.CompositeExtract(value, 1)}, conversion);
|
||||
const auto z = ApplyReadNumberConversion(ir, F32{ir.CompositeExtract(value, 2)}, conversion);
|
||||
const auto w = ApplyReadNumberConversion(ir, F32{ir.CompositeExtract(value, 3)}, conversion);
|
||||
return ir.CompositeConstruct(x, y, z, w);
|
||||
}
|
||||
|
||||
/// Applies a number conversion in the write direction.
|
||||
inline F32 ApplyWriteNumberConversion(IREmitter& ir, const F32& value,
|
||||
const AmdGpu::NumberConversion& conversion) {
|
||||
switch (conversion) {
|
||||
case AmdGpu::NumberConversion::None:
|
||||
return value;
|
||||
case AmdGpu::NumberConversion::UintToUscaled:
|
||||
// Need to return float type to maintain IR semantics.
|
||||
return ir.BitCast<F32>(U32{ir.ConvertFToU(32, value)});
|
||||
case AmdGpu::NumberConversion::SintToSscaled:
|
||||
// Need to return float type to maintain IR semantics.
|
||||
return ir.BitCast<F32>(U32{ir.ConvertFToS(32, value)});
|
||||
case AmdGpu::NumberConversion::UnormToUbnorm:
|
||||
// Convert -1...1 to 0...1
|
||||
return ir.FPDiv(ir.FPAdd(value, ir.Imm32(1.f)), ir.Imm32(2.f));
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
||||
inline Value ApplyWriteNumberConversionVec4(IREmitter& ir, const Value& value,
|
||||
const AmdGpu::NumberConversion& conversion) {
|
||||
if (conversion == AmdGpu::NumberConversion::None) {
|
||||
return value;
|
||||
}
|
||||
const auto x = ApplyWriteNumberConversion(ir, F32{ir.CompositeExtract(value, 0)}, conversion);
|
||||
const auto y = ApplyWriteNumberConversion(ir, F32{ir.CompositeExtract(value, 1)}, conversion);
|
||||
const auto z = ApplyWriteNumberConversion(ir, F32{ir.CompositeExtract(value, 2)}, conversion);
|
||||
const auto w = ApplyWriteNumberConversion(ir, F32{ir.CompositeExtract(value, 3)}, conversion);
|
||||
return ir.CompositeConstruct(x, y, z, w);
|
||||
}
|
||||
|
||||
} // namespace Shader::IR
|
||||
|
|
|
|||
|
|
@ -180,6 +180,7 @@ struct FragmentRuntimeInfo {
|
|||
std::array<PsInput, 32> inputs;
|
||||
struct PsColorBuffer {
|
||||
AmdGpu::NumberFormat num_format;
|
||||
AmdGpu::NumberConversion num_conversion;
|
||||
AmdGpu::CompMapping swizzle;
|
||||
|
||||
auto operator<=>(const PsColorBuffer&) const noexcept = default;
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ struct BufferSpecialization {
|
|||
struct TextureBufferSpecialization {
|
||||
bool is_integer = false;
|
||||
AmdGpu::CompMapping dst_select{};
|
||||
AmdGpu::NumberConversion num_conversion{};
|
||||
|
||||
auto operator<=>(const TextureBufferSpecialization&) const = default;
|
||||
};
|
||||
|
|
@ -41,6 +42,7 @@ struct ImageSpecialization {
|
|||
bool is_integer = false;
|
||||
bool is_storage = false;
|
||||
AmdGpu::CompMapping dst_select{};
|
||||
AmdGpu::NumberConversion num_conversion{};
|
||||
|
||||
auto operator<=>(const ImageSpecialization&) const = default;
|
||||
};
|
||||
|
|
@ -107,6 +109,7 @@ struct StageSpecialization {
|
|||
[](auto& spec, const auto& desc, AmdGpu::Buffer sharp) {
|
||||
spec.is_integer = AmdGpu::IsInteger(sharp.GetNumberFmt());
|
||||
spec.dst_select = sharp.DstSelect();
|
||||
spec.num_conversion = sharp.GetNumberConversion();
|
||||
});
|
||||
ForEachSharp(binding, images, info->images,
|
||||
[](auto& spec, const auto& desc, AmdGpu::Image sharp) {
|
||||
|
|
@ -116,6 +119,7 @@ struct StageSpecialization {
|
|||
if (spec.is_storage) {
|
||||
spec.dst_select = sharp.DstSelect();
|
||||
}
|
||||
spec.num_conversion = sharp.GetNumberConversion();
|
||||
});
|
||||
ForEachSharp(binding, fmasks, info->fmasks,
|
||||
[](auto& spec, const auto& desc, AmdGpu::Image sharp) {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue